Loading...
Searching...
No Matches
periph_cpu_common.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2025 Mesotic SAS
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef PERIPH_CPU_COMMON_H
21#define PERIPH_CPU_COMMON_H
22
23#include "cpu.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#ifndef DOXYGEN
30#define HAVE_GPIO_T
31typedef uint32_t gpio_t;
32
33#define GPIO_UNDEF (0xffffffff)
34
35#define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
36#endif /* DOXYGEN */
37
46#define TIMER_CHANNEL_NUMOF (1)
47
56#define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
57
58#ifndef DOXYGEN
59#define HAVE_GPIO_MODE_T
60typedef enum {
61 GPIO_IN = GPIO_MODE(0, 0, 0),
62 GPIO_IN_PD = 0xf,
63 GPIO_IN_PU = GPIO_MODE(0, 1, 0),
64 GPIO_OUT = GPIO_MODE(1, 0, 0),
65 GPIO_OD = GPIO_MODE(1, 0, 1),
66 GPIO_OD_PU = GPIO_MODE(1, 1, 1),
68
69#define HAVE_GPIO_FLANK_T
70typedef enum {
71 GPIO_RISING = 1,
72 GPIO_FALLING = 2,
73 GPIO_BOTH = 3
75#endif /* ndef DOXYGEN */
76
80typedef enum {
83#ifdef CPU_FAM_SAM4S
84 GPIO_MUX_C = 2,
85 GPIO_MUX_D = 3,
86#endif
88
92enum {
93 PA = 0,
94 PB = 1,
95 PC = 2,
96#ifdef CPU_FAM_SAM3
97 PD = 3,
98#endif
99};
100
108
112typedef struct {
113 Tc *dev;
114 uint8_t id_ch0;
116
120typedef struct {
121 Uart *dev;
122 gpio_t rx_pin;
123 gpio_t tx_pin;
124 gpio_mux_t mux;
125 uint8_t pmc_id;
126 uint8_t irqn;
128
129#ifdef __cplusplus
130}
131#endif
132
133#endif /* PERIPH_CPU_COMMON_H */
gpio_flank_t
Definition periph_cpu.h:180
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:165
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:164
uint16_t gpio_t
GPIO type identifier.
Definition periph_cpu.h:117
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:82
#define GPIO_MODE(oe, ic, pr, dr)
Generate GPIO mode bitfields.
@ PB
port B
@ PC
port C
@ PA
port A
@ PD
port D
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Set up alternate function (PMUX setting) for a PORT pin.
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ GPIO_MUX_A
select peripheral function A
@ GPIO_MUX_B
select peripheral function B
Timer device configuration.
Definition periph_cpu.h:264
Tc * dev
timer device
uint8_t id_ch0
ID of the timer's first channel.
UART device configuration.
Definition periph_cpu.h:218
uint8_t pmc_id
bit in the PMC register of the device
Uart * dev
U(S)ART device used.