Loading...
Searching...
No Matches
periph_cpu_common.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2015-2018 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CPU_COMMON_H
20#define PERIPH_CPU_COMMON_H
21
22#include "cpu.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
31#ifdef NRF_FICR_S
32#define NRF_FICR NRF_FICR_S
33#endif
34
39#ifdef CPU_MODEL_NRF52832XXAA
40#define ERRATA_SPI_SINGLE_BYTE_WORKAROUND (1)
41#endif
42
47#define PROVIDES_PM_OFF
53#ifdef FICR_INFO_DEVICEID_DEVICEID_Msk
54#define CPUID_ADDR (&NRF_FICR->INFO.DEVICEID[0])
55#else
56#define CPUID_ADDR (&NRF_FICR->DEVICEID[0])
57#endif
61#define CPUID_LEN (8U)
62
68#if GPIO_COUNT > 1
69#define GPIO_PIN(x, y) ((x << 5) | y)
70#else
71#define GPIO_PIN(x, y) ((x & 0) | y)
72#endif
73
77/* The precise value matters where GPIO_UNDEF is set in registers like
78 * PWM.PSEL.OUT where it is used in sign-extended form to get a UINT32_MAX */
79#define GPIO_UNDEF (UINT8_MAX)
80
87#ifdef NRF_GPIOTE0_S
88#define ISR_GPIOTE isr_gpiote0
89#else
90#define ISR_GPIOTE isr_gpiote
91#endif
92
102#define GPIO_MODE(oe, ic, pr, dr) (oe | (ic << 1) | (pr << 2) | (dr << 8))
103
104#ifndef DOXYGEN /* BEGIN: GPIO LL overwrites */
105#define HAVE_GPIO_SLEW_T
106typedef enum {
108 GPIO_SLEW_SLOW = 0,
109 GPIO_SLEW_FAST = 0,
112
113#define HAVE_GPIO_PULL_STRENGTH_T
114typedef enum {
116 GPIO_PULL_WEAK = 0,
120
121#define HAVE_GPIO_DRIVE_STRENGTH_T
122typedef enum {
124 GPIO_DRIVE_WEAK = 0,
128
129#define HAVE_GPIO_IRQ_TRIG_T
130typedef enum {
131 GPIO_TRIGGER_EDGE_RISING = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos,
132 GPIO_TRIGGER_EDGE_FALLING = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos,
137
138#define HAVE_GPIO_PULL_T
139typedef enum {
140 GPIO_FLOATING = 0,
141 GPIO_PULL_UP = GPIO_PIN_CNF_PULL_Pullup,
142 GPIO_PULL_DOWN = GPIO_PIN_CNF_PULL_Pulldown,
143 GPIO_PULL_KEEP = 2,
145
146#define HAVE_GPIO_STATE_T
147typedef enum {
155
156#define HAVE_GPIO_CONF_T
157typedef union gpio_conf_nrf5x gpio_conf_t;
158
159#endif
160
166 uint8_t bits;
167 struct {
200 uint8_t : 1; /*< padding */
201 };
202};
203/* END: GPIO LL overwrites */
204
205#if !defined(DOXYGEN) && (defined(CPU_NRF53) || defined(CPU_NRF9160))
209#define UART_BAUDRATE_BAUDRATE_Baud1200 UARTE_BAUDRATE_BAUDRATE_Baud1200
210#define UART_BAUDRATE_BAUDRATE_Baud2400 UARTE_BAUDRATE_BAUDRATE_Baud2400
211#define UART_BAUDRATE_BAUDRATE_Baud4800 UARTE_BAUDRATE_BAUDRATE_Baud4800
212#define UART_BAUDRATE_BAUDRATE_Baud9600 UARTE_BAUDRATE_BAUDRATE_Baud9600
213#define UART_BAUDRATE_BAUDRATE_Baud14400 UARTE_BAUDRATE_BAUDRATE_Baud14400
214#define UART_BAUDRATE_BAUDRATE_Baud19200 UARTE_BAUDRATE_BAUDRATE_Baud19200
215#define UART_BAUDRATE_BAUDRATE_Baud28800 UARTE_BAUDRATE_BAUDRATE_Baud28800
216#define UART_BAUDRATE_BAUDRATE_Baud31250 UARTE_BAUDRATE_BAUDRATE_Baud31250
217#define UART_BAUDRATE_BAUDRATE_Baud38400 UARTE_BAUDRATE_BAUDRATE_Baud38400
218#define UART_BAUDRATE_BAUDRATE_Baud56000 UARTE_BAUDRATE_BAUDRATE_Baud56000
219#define UART_BAUDRATE_BAUDRATE_Baud57600 UARTE_BAUDRATE_BAUDRATE_Baud57600
220#define UART_BAUDRATE_BAUDRATE_Baud76800 UARTE_BAUDRATE_BAUDRATE_Baud76800
221#define UART_BAUDRATE_BAUDRATE_Baud115200 UARTE_BAUDRATE_BAUDRATE_Baud115200
222#define UART_BAUDRATE_BAUDRATE_Baud230400 UARTE_BAUDRATE_BAUDRATE_Baud230400
223#define UART_BAUDRATE_BAUDRATE_Baud250000 UARTE_BAUDRATE_BAUDRATE_Baud250000
224#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
225#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
226#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
227
228#define SPI_FREQUENCY_FREQUENCY_K125 SPIM_FREQUENCY_FREQUENCY_K125
229#define SPI_FREQUENCY_FREQUENCY_K500 SPIM_FREQUENCY_FREQUENCY_K500
230#define SPI_FREQUENCY_FREQUENCY_M1 SPIM_FREQUENCY_FREQUENCY_M1
231#define SPI_FREQUENCY_FREQUENCY_M4 SPIM_FREQUENCY_FREQUENCY_M4
232#define SPI_FREQUENCY_FREQUENCY_M8 SPIM_FREQUENCY_FREQUENCY_M8
233#define SPI_CONFIG_CPHA_Msk SPIM_CONFIG_CPHA_Msk
234#define SPI_CONFIG_CPOL_Msk SPIM_CONFIG_CPOL_Msk
235#endif
236
240#define SPI_HWCS(x) (SPI_CS_UNDEF)
241
246#define PERIPH_SPI_NEEDS_INIT_CS
247#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
248#define PERIPH_SPI_NEEDS_TRANSFER_REG
249#define PERIPH_SPI_NEEDS_TRANSFER_REGS
252#ifndef DOXYGEN
257#define HAVE_GPIO_T
258typedef uint8_t gpio_t;
270#define HAVE_GPIO_MODE_T
271typedef enum {
272 GPIO_IN = GPIO_MODE(0, 0, 0, 0),
273 GPIO_IN_PD = GPIO_MODE(0, 0, 1, 0),
274 GPIO_IN_PU = GPIO_MODE(0, 0, 3, 0),
275 GPIO_IN_OD_PU = GPIO_MODE(0, 0, 3, 6),
276 GPIO_OUT = GPIO_MODE(1, 1, 0, 0),
277 GPIO_OD = (0xff),
278 GPIO_OD_PU = (0xfe)
286#define HAVE_GPIO_FLANK_T
287typedef enum {
288 GPIO_FALLING = 2,
289 GPIO_RISING = 1,
290 GPIO_BOTH = 3
293#endif /* ndef DOXYGEN */
294
298typedef struct {
299 NRF_TIMER_Type *dev;
307 uint8_t channels;
308 uint8_t bitmode;
309 uint8_t irqn;
311
315#define PERIPH_TIMER_PROVIDES_SET 1
316
325#define TIMER_CHANNEL_NUMOF 5
326
327#ifndef DOXYGEN
332#define HAVE_SPI_MODE_T
333typedef enum {
334 SPI_MODE_0 = 0,
335 SPI_MODE_1 = SPI_CONFIG_CPHA_Msk,
336 SPI_MODE_2 = SPI_CONFIG_CPOL_Msk,
337 SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk)
338} spi_mode_t;
345#define HAVE_SPI_CLK_T
346typedef enum {
347 SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125,
348 SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500,
349 SPI_CLK_1MHZ = SPI_FREQUENCY_FREQUENCY_M1,
350 SPI_CLK_5MHZ = SPI_FREQUENCY_FREQUENCY_M4,
351 SPI_CLK_10MHZ = SPI_FREQUENCY_FREQUENCY_M8
352} spi_clk_t;
354#endif /* ndef DOXYGEN */
355
360#define NWDT_TIME_LOWER_LIMIT (1)
361/* Set upper limit to the maximum possible value that could go in CRV register */
362#define NWDT_TIME_UPPER_LIMIT ((UINT32_MAX >> 15) * US_PER_MS + 1)
368typedef struct {
369 gpio_t a_pin;
370 gpio_t b_pin;
371 gpio_t led_pin;
375
384uint8_t gpio_int_get_exti(gpio_t pin);
385
389typedef struct {
390#ifdef UARTE_PRESENT
391 NRF_UARTE_Type *dev;
393#else
394 NRF_UART_Type *dev;
395#endif
396 gpio_t rx_pin;
397 gpio_t tx_pin;
398#ifdef MODULE_PERIPH_UART_HW_FC
399 gpio_t rts_pin;
400 gpio_t cts_pin;
401#endif
402 uint8_t irqn;
404
408#ifndef UART_TXBUF_SIZE
409#define UART_TXBUF_SIZE (64)
410#endif
411
415#define USBDEV_CPU_DMA_ALIGNMENT (4)
416
420#define USBDEV_CPU_DMA_REQUIREMENTS __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
421
422#if !defined(CPU_FAM_NRF51) && !defined(DOXYGEN)
427#define PWM_CHANNELS (4U)
428
436#define PWM_MODE(ud, pol) (ud | (pol << 15))
437
441#define HAVE_PWM_MODE_T
442typedef enum {
443 PWM_LEFT = PWM_MODE(0, 1),
444 PWM_RIGHT = PWM_MODE(0, 0),
445 PWM_CENTER = PWM_MODE(1, 1),
446 PWM_CENTER_INV = PWM_MODE(1, 0)
447} pwm_mode_t;
448
463#if defined(PWM_PRESENT)
464typedef struct {
465 NRF_PWM_Type *dev;
466 gpio_t pin[PWM_CHANNELS];
467} pwm_conf_t;
468#endif
469#endif /* ndef CPU_FAM_NRF51 */
470#ifndef CPU_NRF51
471
475#define SPI_SCKSEL (dev(bus)->PSEL.SCK)
476#define SPI_MOSISEL (dev(bus)->PSEL.MOSI)
477#define SPI_MISOSEL (dev(bus)->PSEL.MISO)
482typedef struct {
483 NRF_SPIM_Type *dev;
484 gpio_t sclk;
485 gpio_t mosi;
486 gpio_t miso;
487#if ERRATA_SPI_SINGLE_BYTE_WORKAROUND
488 uint8_t ppi;
489#endif
490} spi_conf_t;
491
497typedef void (*shared_irq_cb_t)(void *arg);
498
506void shared_irq_register_spi(NRF_SPIM_Type *bus,
507 shared_irq_cb_t cb, void *arg);
508
516void shared_irq_register_i2c(NRF_TWIM_Type *bus,
517 shared_irq_cb_t cb, void *arg);
518
526void shared_irq_register_uart(NRF_UARTE_Type *bus,
527 shared_irq_cb_t cb, void *arg);
528
536void nrf5x_i2c_acquire(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg);
537
543void nrf5x_i2c_release(NRF_TWIM_Type *bus);
544
552void nrf5x_spi_acquire(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg);
553
559void nrf5x_spi_release(NRF_SPIM_Type *bus);
560
564#ifndef UART_TXBUF_SIZE
565#define UART_TXBUF_SIZE (64)
566#endif
567
572#ifndef CONFIG_SPI_MBUF_SIZE
573#define CONFIG_SPI_MBUF_SIZE 64
574#endif
575
576#ifndef DOXYGEN
581#define HAVE_I2C_SPEED_T
582typedef enum {
583 I2C_SPEED_LOW = 0xff,
584 I2C_SPEED_NORMAL = TWIM_FREQUENCY_FREQUENCY_K100,
585 I2C_SPEED_FAST = TWIM_FREQUENCY_FREQUENCY_K400,
586 I2C_SPEED_FAST_PLUS = 0xfe,
587 I2C_SPEED_HIGH = 0xfd,
590#endif /* ndef DOXYGEN */
591
596typedef struct {
597 NRF_TWIM_Type *dev;
598 gpio_t scl;
599 gpio_t sda;
600 i2c_speed_t speed;
601} i2c_conf_t;
608#define PERIPH_I2C_NEED_READ_REG
609#define PERIPH_I2C_NEED_WRITE_REG
616#define i2c_pin_sda(dev) i2c_config[dev].sda
617#define i2c_pin_scl(dev) i2c_config[dev].scl
619#endif /* ndef CPU_NRF51 */
620
621#ifdef __cplusplus
622}
623#endif
624
625#endif /* PERIPH_CPU_COMMON_H */
gpio_flank_t
Definition periph_cpu.h:180
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:165
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:164
i2c_speed_t
Definition periph_cpu.h:276
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition periph_cpu.h:280
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition periph_cpu.h:277
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition periph_cpu.h:282
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:279
spi_clk_t
Definition periph_cpu.h:352
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:357
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:356
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:354
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:355
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:353
pwm_mode_t
@ PWM_CENTER
center aligned
@ PWM_LEFT
left aligned
@ PWM_RIGHT
right aligned
gpio_irq_trig_t
Definition of possible IRQ triggers.
Definition gpio_ll_irq.h:72
@ GPIO_TRIGGER_EDGE_FALLING
edge triggered IRQ on falling flanks only
Definition gpio_ll_irq.h:73
@ GPIO_TRIGGER_LEVEL_HIGH
level triggered IRQ on high input
Definition gpio_ll_irq.h:78
@ GPIO_TRIGGER_EDGE_RISING
edge triggered IRQ on rising flanks only
Definition gpio_ll_irq.h:75
@ GPIO_TRIGGER_EDGE_BOTH
edge triggered IRQ on falling AND rising flanks
Definition gpio_ll_irq.h:76
@ GPIO_TRIGGER_LEVEL_LOW
level triggered IRQ on low input
Definition gpio_ll_irq.h:79
gpio_pull_t
Enumeration of pull resistor configurations.
Definition gpio_ll.h:250
gpio_pull_strength_t
Enumeration of pull resistor values.
Definition gpio_ll.h:268
gpio_state_t
Enumeration of GPIO states (direction)
Definition gpio_ll.h:158
gpio_slew_t
Enumeration of slew rate settings.
Definition gpio_ll.h:332
gpio_drive_strength_t
Enumeration of drive strength options.
Definition gpio_ll.h:299
typedef gpio_conf_t
GPIO pin configuration.
Definition gpio_ll.h:416
@ GPIO_FLOATING
No pull ups nor pull downs enabled.
Definition gpio_ll.h:251
@ GPIO_PULL_KEEP
Keep the signal at current logic level with pull up/down resistors.
Definition gpio_ll.h:254
@ GPIO_PULL_DOWN
Pull down resistor enabled.
Definition gpio_ll.h:253
@ GPIO_PULL_UP
Pull up resistor enabled.
Definition gpio_ll.h:252
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
Definition gpio_ll.h:269
@ GPIO_PULL_WEAK
Use a weak pull resistor.
Definition gpio_ll.h:270
@ GPIO_PULL_STRONG
Use a strong pull resistor.
Definition gpio_ll.h:271
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
Definition gpio_ll.h:272
@ GPIO_OUTPUT_OPEN_SOURCE
Use pin as output in open emitter configuration.
Definition gpio_ll.h:195
@ GPIO_USED_BY_PERIPHERAL
The GPIO pin is used by a peripheral.
Definition gpio_ll.h:214
@ GPIO_OUTPUT_OPEN_DRAIN
Use pin as output in open collector configuration.
Definition gpio_ll.h:182
@ GPIO_OUTPUT_PUSH_PULL
Use pin as output in push-pull configuration.
Definition gpio_ll.h:169
@ GPIO_DISCONNECT
Disconnect pin from all peripherals.
Definition gpio_ll.h:242
@ GPIO_INPUT
Use pin as input.
Definition gpio_ll.h:201
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
Definition gpio_ll.h:333
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
Definition gpio_ll.h:336
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
Definition gpio_ll.h:335
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
Definition gpio_ll.h:337
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
Definition gpio_ll.h:302
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
Definition gpio_ll.h:301
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
Definition gpio_ll.h:303
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
Definition gpio_ll.h:300
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:82
void nrf5x_i2c_acquire(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg)
Acquire the shared I2C/SPI peripheral in I2C mode.
uint8_t gpio_int_get_exti(gpio_t pin)
Retrieve the exti(GPIOTE) channel associated with a gpio.
void shared_irq_register_i2c(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg)
Register an I2C IRQ handler for a shared UART/I2C/SPI irq vector.
void nrf5x_spi_release(NRF_SPIM_Type *bus)
Acquire the shared I2C/SPI peripheral in SPI mode.
void(* shared_irq_cb_t)(void *arg)
Common UART/SPI/I2C interrupt callback.
#define GPIO_MODE(oe, ic, pr, dr)
Generate GPIO mode bitfields.
void nrf5x_spi_acquire(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg)
Acquire the shared I2C/SPI peripheral in SPI mode.
void shared_irq_register_spi(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg)
Register a SPI IRQ handler for a shared UART/I2C/SPI irq vector.
void shared_irq_register_uart(NRF_UARTE_Type *bus, shared_irq_cb_t cb, void *arg)
Register an UART IRQ handler for a shared UART/I2C/SPI irq vector.
void nrf5x_i2c_release(NRF_TWIM_Type *bus)
Release the shared I2C/SPI peripheral in I2C mode.
I2C configuration structure.
Definition periph_cpu.h:299
NRF_TWIM_Type * dev
TWIM hardware device.
PWM device configuration.
Quadrature decoder configuration struct.
bool debounce_filter
Enable/disable debounce filter.
gpio_t b_pin
GPIO Pin for phase B.
gpio_t a_pin
GPIO Pin for phase A.
gpio_t led_pin
LED GPIO, GPIO_UNDEF to disable.
uint8_t sample_period
Sample period used, e.g.
SPI device configuration.
Definition periph_cpu.h:337
NRF_SPIM_Type * dev
SPI device used.
Timer device configuration.
Definition periph_cpu.h:264
uint8_t channels
number of hardware channels minus one
uint8_t bitmode
counter width
NRF_TIMER_Type * dev
timer device
UART device configuration.
Definition periph_cpu.h:218
NRF_UART_Type * dev
UART device base register address.
GPIO pin configuration for nRF5x MCUs.
gpio_pull_t pull
Pull resistor configuration.
gpio_drive_strength_t drive_strength
Drive strength of the GPIO.
gpio_state_t state
State of the pin.
bool initial_value
Initial value of the output.
uint8_t bits
the raw bits