19#ifndef PERIPH_CPU_COMMON_H
20#define PERIPH_CPU_COMMON_H
32#define NRF_FICR NRF_FICR_S
39#ifdef CPU_MODEL_NRF52832XXAA
40#define ERRATA_SPI_SINGLE_BYTE_WORKAROUND (1)
47#define PROVIDES_PM_OFF
53#ifdef FICR_INFO_DEVICEID_DEVICEID_Msk
54#define CPUID_ADDR (&NRF_FICR->INFO.DEVICEID[0])
56#define CPUID_ADDR (&NRF_FICR->DEVICEID[0])
69#define GPIO_PIN(x, y) ((x << 5) | y)
71#define GPIO_PIN(x, y) ((x & 0) | y)
79#define GPIO_UNDEF (UINT8_MAX)
88#define ISR_GPIOTE isr_gpiote0
90#define ISR_GPIOTE isr_gpiote
102#define GPIO_MODE(oe, ic, pr, dr) (oe | (ic << 1) | (pr << 2) | (dr << 8))
105#define HAVE_GPIO_SLEW_T
113#define HAVE_GPIO_PULL_STRENGTH_T
121#define HAVE_GPIO_DRIVE_STRENGTH_T
129#define HAVE_GPIO_IRQ_TRIG_T
138#define HAVE_GPIO_PULL_T
146#define HAVE_GPIO_STATE_T
156#define HAVE_GPIO_CONF_T
205#if !defined(DOXYGEN) && (defined(CPU_NRF53) || defined(CPU_NRF9160))
209#define UART_BAUDRATE_BAUDRATE_Baud1200 UARTE_BAUDRATE_BAUDRATE_Baud1200
210#define UART_BAUDRATE_BAUDRATE_Baud2400 UARTE_BAUDRATE_BAUDRATE_Baud2400
211#define UART_BAUDRATE_BAUDRATE_Baud4800 UARTE_BAUDRATE_BAUDRATE_Baud4800
212#define UART_BAUDRATE_BAUDRATE_Baud9600 UARTE_BAUDRATE_BAUDRATE_Baud9600
213#define UART_BAUDRATE_BAUDRATE_Baud14400 UARTE_BAUDRATE_BAUDRATE_Baud14400
214#define UART_BAUDRATE_BAUDRATE_Baud19200 UARTE_BAUDRATE_BAUDRATE_Baud19200
215#define UART_BAUDRATE_BAUDRATE_Baud28800 UARTE_BAUDRATE_BAUDRATE_Baud28800
216#define UART_BAUDRATE_BAUDRATE_Baud31250 UARTE_BAUDRATE_BAUDRATE_Baud31250
217#define UART_BAUDRATE_BAUDRATE_Baud38400 UARTE_BAUDRATE_BAUDRATE_Baud38400
218#define UART_BAUDRATE_BAUDRATE_Baud56000 UARTE_BAUDRATE_BAUDRATE_Baud56000
219#define UART_BAUDRATE_BAUDRATE_Baud57600 UARTE_BAUDRATE_BAUDRATE_Baud57600
220#define UART_BAUDRATE_BAUDRATE_Baud76800 UARTE_BAUDRATE_BAUDRATE_Baud76800
221#define UART_BAUDRATE_BAUDRATE_Baud115200 UARTE_BAUDRATE_BAUDRATE_Baud115200
222#define UART_BAUDRATE_BAUDRATE_Baud230400 UARTE_BAUDRATE_BAUDRATE_Baud230400
223#define UART_BAUDRATE_BAUDRATE_Baud250000 UARTE_BAUDRATE_BAUDRATE_Baud250000
224#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
225#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
226#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
228#define SPI_FREQUENCY_FREQUENCY_K125 SPIM_FREQUENCY_FREQUENCY_K125
229#define SPI_FREQUENCY_FREQUENCY_K500 SPIM_FREQUENCY_FREQUENCY_K500
230#define SPI_FREQUENCY_FREQUENCY_M1 SPIM_FREQUENCY_FREQUENCY_M1
231#define SPI_FREQUENCY_FREQUENCY_M4 SPIM_FREQUENCY_FREQUENCY_M4
232#define SPI_FREQUENCY_FREQUENCY_M8 SPIM_FREQUENCY_FREQUENCY_M8
233#define SPI_CONFIG_CPHA_Msk SPIM_CONFIG_CPHA_Msk
234#define SPI_CONFIG_CPOL_Msk SPIM_CONFIG_CPOL_Msk
240#define SPI_HWCS(x) (SPI_CS_UNDEF)
246#define PERIPH_SPI_NEEDS_INIT_CS
247#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
248#define PERIPH_SPI_NEEDS_TRANSFER_REG
249#define PERIPH_SPI_NEEDS_TRANSFER_REGS
258typedef uint8_t gpio_t;
270#define HAVE_GPIO_MODE_T
286#define HAVE_GPIO_FLANK_T
315#define PERIPH_TIMER_PROVIDES_SET 1
325#define TIMER_CHANNEL_NUMOF 5
332#define HAVE_SPI_MODE_T
337 SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk)
345#define HAVE_SPI_CLK_T
360#define NWDT_TIME_LOWER_LIMIT (1)
362#define NWDT_TIME_UPPER_LIMIT ((UINT32_MAX >> 15) * US_PER_MS + 1)
398#ifdef MODULE_PERIPH_UART_HW_FC
408#ifndef UART_TXBUF_SIZE
409#define UART_TXBUF_SIZE (64)
415#define USBDEV_CPU_DMA_ALIGNMENT (4)
420#define USBDEV_CPU_DMA_REQUIREMENTS __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
422#if !defined(CPU_FAM_NRF51) && !defined(DOXYGEN)
427#define PWM_CHANNELS (4U)
436#define PWM_MODE(ud, pol) (ud | (pol << 15))
441#define HAVE_PWM_MODE_T
446 PWM_CENTER_INV = PWM_MODE(1, 0)
463#if defined(PWM_PRESENT)
466 gpio_t pin[PWM_CHANNELS];
475#define SPI_SCKSEL (dev(bus)->PSEL.SCK)
476#define SPI_MOSISEL (dev(bus)->PSEL.MOSI)
477#define SPI_MISOSEL (dev(bus)->PSEL.MISO)
487#if ERRATA_SPI_SINGLE_BYTE_WORKAROUND
564#ifndef UART_TXBUF_SIZE
565#define UART_TXBUF_SIZE (64)
572#ifndef CONFIG_SPI_MBUF_SIZE
573#define CONFIG_SPI_MBUF_SIZE 64
581#define HAVE_I2C_SPEED_T
608#define PERIPH_I2C_NEED_READ_REG
609#define PERIPH_I2C_NEED_WRITE_REG
616#define i2c_pin_sda(dev) i2c_config[dev].sda
617#define i2c_pin_scl(dev) i2c_config[dev].scl
@ GPIO_OUT
select GPIO MASK as output
@ GPIO_IN
select GPIO MASK as input
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
@ PWM_CENTER
center aligned
gpio_irq_trig_t
Definition of possible IRQ triggers.
@ GPIO_TRIGGER_EDGE_FALLING
edge triggered IRQ on falling flanks only
@ GPIO_TRIGGER_LEVEL_HIGH
level triggered IRQ on high input
@ GPIO_TRIGGER_EDGE_RISING
edge triggered IRQ on rising flanks only
@ GPIO_TRIGGER_EDGE_BOTH
edge triggered IRQ on falling AND rising flanks
@ GPIO_TRIGGER_LEVEL_LOW
level triggered IRQ on low input
gpio_pull_t
Enumeration of pull resistor configurations.
gpio_pull_strength_t
Enumeration of pull resistor values.
gpio_state_t
Enumeration of GPIO states (direction)
gpio_slew_t
Enumeration of slew rate settings.
gpio_drive_strength_t
Enumeration of drive strength options.
typedef gpio_conf_t
GPIO pin configuration.
@ GPIO_FLOATING
No pull ups nor pull downs enabled.
@ GPIO_PULL_KEEP
Keep the signal at current logic level with pull up/down resistors.
@ GPIO_PULL_DOWN
Pull down resistor enabled.
@ GPIO_PULL_UP
Pull up resistor enabled.
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
@ GPIO_PULL_WEAK
Use a weak pull resistor.
@ GPIO_PULL_STRONG
Use a strong pull resistor.
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
@ GPIO_OUTPUT_OPEN_SOURCE
Use pin as output in open emitter configuration.
@ GPIO_USED_BY_PERIPHERAL
The GPIO pin is used by a peripheral.
@ GPIO_OUTPUT_OPEN_DRAIN
Use pin as output in open collector configuration.
@ GPIO_OUTPUT_PUSH_PULL
Use pin as output in push-pull configuration.
@ GPIO_DISCONNECT
Disconnect pin from all peripherals.
@ GPIO_INPUT
Use pin as input.
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
spi_mode_t
Support SPI modes.
@ SPI_MODE_0
CPOL=0, CPHA=0.
@ SPI_MODE_2
CPOL=1, CPHA=0.
@ SPI_MODE_1
CPOL=0, CPHA=1.
@ SPI_MODE_3
CPOL=1, CPHA=1.
gpio_mode_t
Available pin modes.
void nrf5x_i2c_acquire(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg)
Acquire the shared I2C/SPI peripheral in I2C mode.
uint8_t gpio_int_get_exti(gpio_t pin)
Retrieve the exti(GPIOTE) channel associated with a gpio.
void shared_irq_register_i2c(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg)
Register an I2C IRQ handler for a shared UART/I2C/SPI irq vector.
void nrf5x_spi_release(NRF_SPIM_Type *bus)
Acquire the shared I2C/SPI peripheral in SPI mode.
void(* shared_irq_cb_t)(void *arg)
Common UART/SPI/I2C interrupt callback.
#define GPIO_MODE(oe, ic, pr, dr)
Generate GPIO mode bitfields.
void nrf5x_spi_acquire(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg)
Acquire the shared I2C/SPI peripheral in SPI mode.
void shared_irq_register_spi(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg)
Register a SPI IRQ handler for a shared UART/I2C/SPI irq vector.
void shared_irq_register_uart(NRF_UARTE_Type *bus, shared_irq_cb_t cb, void *arg)
Register an UART IRQ handler for a shared UART/I2C/SPI irq vector.
void nrf5x_i2c_release(NRF_TWIM_Type *bus)
Release the shared I2C/SPI peripheral in I2C mode.
I2C configuration structure.
NRF_TWIM_Type * dev
TWIM hardware device.
PWM device configuration.
Quadrature decoder configuration struct.
bool debounce_filter
Enable/disable debounce filter.
gpio_t b_pin
GPIO Pin for phase B.
gpio_t a_pin
GPIO Pin for phase A.
gpio_t led_pin
LED GPIO, GPIO_UNDEF to disable.
uint8_t sample_period
Sample period used, e.g.
SPI device configuration.
NRF_SPIM_Type * dev
SPI device used.
Timer device configuration.
uint8_t channels
number of hardware channels minus one
uint8_t bitmode
counter width
NRF_TIMER_Type * dev
timer device
UART device configuration.
NRF_UART_Type * dev
UART device base register address.
GPIO pin configuration for nRF5x MCUs.
gpio_pull_t pull
Pull resistor configuration.
gpio_drive_strength_t drive_strength
Drive strength of the GPIO.
gpio_state_t state
State of the pin.
bool initial_value
Initial value of the output.