Register definitions for W5500 devices. More...

Detailed Description

Register definitions for W5500 devices.

Author: Stefan Schmidt stems.nosp@m.chmi.nosp@m.dt@gm.nosp@m.ail..nosp@m.com

Definition in file w5500_regs.h.

Macros
#define	Sn_RXBUF_SIZE_BASE (0x001E)
	Register to configure a sockets RX buffer size.

#define	Sn_TXBUF_SIZE_BASE (0x001F)
	Register to configure a sockets TX buffer size.

Common registers (with BSB 00000 in the upper 5 bits).
#define	REG_MODE (0x0000)
	Mode.

#define	REG_GAR0 (0x0001)
	Gateway address 0.

#define	REG_GAR1 (0x0002)
	Gateway address 1.

#define	REG_GAR2 (0x0003)
	Gateway address 2.

#define	REG_GAR3 (0x0004)
	Gateway address 3.

#define	REG_SUBR0 (0x0005)
	Subnet mask 0.

#define	REG_SUBR1 (0x0006)
	Subnet mask 1.

#define	REG_SUBR2 (0x0007)
	Subnet mask 2.

#define	REG_SUBR3 (0x0008)
	Subnet mask 3.

#define	REG_SHAR0 (0x0009)
	Source hardware address 0.

#define	REG_SHAR1 (0x000a)
	Source hardware address 1.

#define	REG_SHAR2 (0x000b)
	Source hardware address 2.

#define	REG_SHAR3 (0x000c)
	Source hardware address 3.

#define	REG_SHAR4 (0x000d)
	Source hardware address 4.

#define	REG_SHAR5 (0x000e)
	Source hardware address 5.

#define	REG_SIPR0 (0x000f)
	Source IP address 0.

#define	REG_SIPR1 (0x0010)
	Source IP address 1.

#define	REG_SIPR2 (0x0011)
	Source IP address 2.

#define	REG_SIPR3 (0x0012)
	Source IP address 3.

#define	REG_INTLEVEL0 (0x0013)
	Interrupt low level timer 0.

#define	REG_INTLEVEL1 (0x0014)
	Interrupt low level timer 1.

#define	REG_IR (0x0015)
	Interrupt flags.

#define	REG_IMR (0x0016)
	Interrupt masks.

#define	REG_SIR (0x0017)
	Socket interrupt.

#define	REG_SIMR (0x0018)
	Socket interrupt mask.

#define	REG_RTR0 (0x0019)
	Retry time 0.

#define	REG_RTR1 (0x001a)
	Retry time 1.

#define	REG_RCR (0x001b)
	Retry count.

#define	REG_PTIMER (0x001c)
	Ppp lcp request timer.

#define	REG_PMAGIC (0x001d)
	Ppp lcp magic number.

#define	REG_PHAR0 (0x001e)
	Ppp destination mac address 0.

#define	REG_PHAR1 (0x001f)
	Ppp destination mac address 1.

#define	REG_PHAR2 (0x0020)
	Ppp destination mac address 2.

#define	REG_PHAR3 (0x0021)
	Ppp destination mac address 3.

#define	REG_PHAR4 (0x0022)
	Ppp destination mac address 4.

#define	REG_PHAR5 (0x0023)
	Ppp destination mac address 5.

#define	REG_PSID0 (0x0024)
	Ppp session identification 0.

#define	REG_PSID1 (0x0025)
	Ppp session identification 1.

#define	REG_PMRU0 (0x0026)
	Ppp maximum segment size 0.

#define	REG_PMRU1 (0x0027)
	Ppp maximum segment size 1.

#define	REG_UIPR0 (0x0028)
	Unreachable IP address 0.

#define	REG_UIPR1 (0x0029)
	Unreachable IP address 1.

#define	REG_UIPR2 (0x002a)
	Unreachable IP address 2.

#define	REG_UIPR3 (0x002b)
	Unreachable IP address 3.

#define	REG_UPORT0 (0x002c)
	Unreachable port 0.

#define	REG_UPORT1 (0x002d)
	Unreachable port 1.

#define	REG_PHYCFGR (0x002e)
	Phy configuration.

#define	REG_VERSIONR (0x0039)
	Chip version.

Socket 0 register block (with BSB 00001 in the upper 5 bits).
#define	REG_S0_MR (0x0800)
	Socket 0 mode.

#define	REG_S0_CR (0x0801)
	Socket 0 command.

#define	REG_S0_IR (0x0802)
	Socket 0 interrupt.

#define	REG_S0_SR (0x0803)
	Socket 0 status.

#define	REG_S0_PORT0 (0x0804)
	Socket 0 Source port 0.

#define	REG_S0_PORT1 (0x0805)
	Socket 0 Source port 1.

#define	REG_S0_DHAR0 (0x0806)
	Socket 0 destination hardware address 0.

#define	REG_S0_DHAR1 (0x0807)
	Socket 0 destination hardware address 1.

#define	REG_S0_DHAR2 (0x0808)
	Socket 0 destination hardware address 2.

#define	REG_S0_DHAR3 (0x0809)
	Socket 0 destination hardware address 3.

#define	REG_S0_DHAR4 (0x080a)
	Socket 0 destination hardware address 4.

#define	REG_S0_DHAR5 (0x080b)
	Socket 0 destination hardware address 5.

#define	REG_S0_DIPR0 (0x080c)
	Socket 0 destination IP address 0.

#define	REG_S0_DIPR1 (0x080d)
	Socket 0 destination IP address 1.

#define	REG_S0_DIPR2 (0x080e)
	Socket 0 destination IP address 2.

#define	REG_S0_DIPR3 (0x080f)
	Socket 0 destination IP address 3.

#define	REG_S0_DPORT0 (0x0810)
	Socket 0 destination port 0.

#define	REG_S0_DPORT1 (0x0811)
	Socket 0 destination port 1.

#define	REG_S0_MSSR0 (0x0812)
	Socket 0 maximum segment size 0.

#define	REG_S0_MSSR1 (0x0813)
	Socket 0 maximum segment size 1.

#define	REG_S0_TOS (0x0815)
	Socket 0 IP TOS.

#define	REG_S0_TTL (0x0816)
	Socket 0 IP TTL.

#define	REG_S0_RXBUF_SIZE (0x081e)
	Socket 0 receive buffer size.

#define	REG_S0_TXBUF_SIZE (0x081f)
	Socket 0 transmit buffer size.

#define	REG_S0_TX_FSR0 (0x0820)
	Socket 0 tx free size 0.

#define	REG_S0_TX_FSR1 (0x0821)
	Socket 0 tx free size 1.

#define	REG_S0_TX_RD0 (0x0822)
	Socket 0 tx read pointer 0.

#define	REG_S0_TX_RD1 (0x0823)
	Socket 0 tx read pointer 1.

#define	REG_S0_TX_WR0 (0x0824)
	Socket 0 tx write pointer 0.

#define	REG_S0_TX_WR1 (0x0825)
	Socket 0 tx write pointer 1.

#define	REG_S0_RX_RSR0 (0x0826)
	Socket 0 rx received size 0.

#define	REG_S0_RX_RSR1 (0x0827)
	Socket 0 rx received size 1.

#define	REG_S0_RX_RD0 (0x0828)
	Socket 0 rx read pointer 0.

#define	REG_S0_RX_RD1 (0x0829)
	Socket 0 rx read pointer 1.

#define	REG_S0_RX_WR0 (0x082a)
	Socket 0 rx write pointer 0.

#define	REG_S0_RX_WR1 (0x082b)
	Socket 0 rx write pointer 1.

#define	REG_S0_IMR (0x082c)
	Socket 0 interrupt mask.

#define	REG_S0_FRAG0 (0x082d)
	Socket 0 fragment offset in IP header 0.

#define	REG_S0_FRAG1 (0x082e)
	Socket 0 fragment offset in IP header 1.

#define	REG_S0_KPALVTR (0x082f)
	Socket 0 keep alive timer.

Some selected bitfield definitions.
#define	MODE_RESET (0x80)
	Device mode: reset.

#define	PHY_LINK_UP (0x01)
	Link up indication.

#define	IMR_S0_INT (0x01)
	Global Socket 0 interrupt mask.

#define	SPI_CONF SPI_MODE_0
	Configure SPI MODE 0.

#define	CHIP_VERSION (0x04)
	Chip version we expect to read from the device.

#define	ENABLE_MAC_FILTER (0x80)
	Enable hardware MAC filter for raw mode.

#define	ENABLE_BROADCAST_FILTER (0x40)
	Enable Broadcast blocking.

#define	ENABLE_MULTICAST_FILTER (0x20)
	Enable Multicast blocking.

#define	MR_MACRAW (0x04)
	Socket mode: raw Ethernet.

#define	CR_OPEN (0x01)
	Socket command: open.

#define	CR_SEND (0x20)
	Socket command: send.

#define	CR_RECV (0x40)
	Socket command: receive new data.

#define	IR_RECV (0x04)
	Socket interrupt: data received.

#define	IR_SEND_OK (0x10)
	Socket interrupt: send ok.

#define	CMD_READ (0x00)
	Define for the read command.

#define	CMD_WRITE (0x04)
	Define for the write command.

#define	SOCKET0_RX_BUFFER (0x18)
	BSB for Socket 0 Receive Buffer.

#define	SOCKET0_TX_BUFFER (0x10)
	BSB for Socket 0 Transmit Buffer.

Macro Definition Documentation

◆ CHIP_VERSION

#define CHIP_VERSION (0x04)

Chip version we expect to read from the device.

Definition at line 152 of file w5500_regs.h.

◆ CMD_READ

#define CMD_READ (0x00)

Define for the read command.

Definition at line 166 of file w5500_regs.h.

◆ CMD_WRITE

#define CMD_WRITE (0x04)

Define for the write command.

Definition at line 167 of file w5500_regs.h.

◆ CR_OPEN

#define CR_OPEN (0x01)

Socket command: open.

Definition at line 159 of file w5500_regs.h.

◆ CR_RECV

#define CR_RECV (0x40)

Socket command: receive new data.

Definition at line 161 of file w5500_regs.h.

◆ CR_SEND

#define CR_SEND (0x20)

Socket command: send.

Definition at line 160 of file w5500_regs.h.

◆ ENABLE_BROADCAST_FILTER

#define ENABLE_BROADCAST_FILTER (0x40)

Enable Broadcast blocking.

Definition at line 155 of file w5500_regs.h.

◆ ENABLE_MAC_FILTER

#define ENABLE_MAC_FILTER (0x80)

Enable hardware MAC filter for raw mode.

Definition at line 154 of file w5500_regs.h.

◆ ENABLE_MULTICAST_FILTER

#define ENABLE_MULTICAST_FILTER (0x20)

Enable Multicast blocking.

Definition at line 156 of file w5500_regs.h.

◆ IMR_S0_INT

#define IMR_S0_INT (0x01)

Global Socket 0 interrupt mask.

Definition at line 150 of file w5500_regs.h.

◆ IR_RECV

#define IR_RECV (0x04)

Socket interrupt: data received.

Definition at line 163 of file w5500_regs.h.

◆ IR_SEND_OK

#define IR_SEND_OK (0x10)

Socket interrupt: send ok.

Definition at line 164 of file w5500_regs.h.

◆ MODE_RESET

#define MODE_RESET (0x80)

Device mode: reset.

Definition at line 148 of file w5500_regs.h.

◆ MR_MACRAW

#define MR_MACRAW (0x04)

Socket mode: raw Ethernet.

Definition at line 157 of file w5500_regs.h.

◆ PHY_LINK_UP

#define PHY_LINK_UP (0x01)

Link up indication.

Definition at line 149 of file w5500_regs.h.

◆ REG_GAR0

#define REG_GAR0 (0x0001)

Gateway address 0.

Definition at line 45 of file w5500_regs.h.

◆ REG_GAR1

#define REG_GAR1 (0x0002)

Gateway address 1.

Definition at line 46 of file w5500_regs.h.

◆ REG_GAR2

#define REG_GAR2 (0x0003)

Gateway address 2.

Definition at line 47 of file w5500_regs.h.

◆ REG_GAR3

#define REG_GAR3 (0x0004)

Gateway address 3.

Definition at line 48 of file w5500_regs.h.

◆ REG_IMR

#define REG_IMR (0x0016)

Interrupt masks.

Definition at line 66 of file w5500_regs.h.

◆ REG_INTLEVEL0

#define REG_INTLEVEL0 (0x0013)

Interrupt low level timer 0.

Definition at line 63 of file w5500_regs.h.

◆ REG_INTLEVEL1

#define REG_INTLEVEL1 (0x0014)

Interrupt low level timer 1.

Definition at line 64 of file w5500_regs.h.

◆ REG_IR

#define REG_IR (0x0015)

Interrupt flags.

Definition at line 65 of file w5500_regs.h.

◆ REG_MODE

#define REG_MODE (0x0000)

Mode.

Definition at line 44 of file w5500_regs.h.

◆ REG_PHAR0

#define REG_PHAR0 (0x001e)

Ppp destination mac address 0.

Definition at line 74 of file w5500_regs.h.

◆ REG_PHAR1

#define REG_PHAR1 (0x001f)

Ppp destination mac address 1.

Definition at line 75 of file w5500_regs.h.

◆ REG_PHAR2

#define REG_PHAR2 (0x0020)

Ppp destination mac address 2.

Definition at line 76 of file w5500_regs.h.

◆ REG_PHAR3

#define REG_PHAR3 (0x0021)

Ppp destination mac address 3.

Definition at line 77 of file w5500_regs.h.

◆ REG_PHAR4

#define REG_PHAR4 (0x0022)

Ppp destination mac address 4.

Definition at line 78 of file w5500_regs.h.

◆ REG_PHAR5

#define REG_PHAR5 (0x0023)

Ppp destination mac address 5.

Definition at line 79 of file w5500_regs.h.

◆ REG_PHYCFGR

#define REG_PHYCFGR (0x002e)

Phy configuration.

Definition at line 90 of file w5500_regs.h.

◆ REG_PMAGIC

#define REG_PMAGIC (0x001d)

Ppp lcp magic number.

Definition at line 73 of file w5500_regs.h.

◆ REG_PMRU0

#define REG_PMRU0 (0x0026)

Ppp maximum segment size 0.

Definition at line 82 of file w5500_regs.h.

◆ REG_PMRU1

#define REG_PMRU1 (0x0027)

Ppp maximum segment size 1.

Definition at line 83 of file w5500_regs.h.

◆ REG_PSID0

#define REG_PSID0 (0x0024)

Ppp session identification 0.

Definition at line 80 of file w5500_regs.h.

◆ REG_PSID1

#define REG_PSID1 (0x0025)

Ppp session identification 1.

Definition at line 81 of file w5500_regs.h.

◆ REG_PTIMER

#define REG_PTIMER (0x001c)

Ppp lcp request timer.

Definition at line 72 of file w5500_regs.h.

◆ REG_RCR

#define REG_RCR (0x001b)

Retry count.

Definition at line 71 of file w5500_regs.h.

◆ REG_RTR0

#define REG_RTR0 (0x0019)

Retry time 0.

Definition at line 69 of file w5500_regs.h.

◆ REG_RTR1

#define REG_RTR1 (0x001a)

Retry time 1.

Definition at line 70 of file w5500_regs.h.

◆ REG_S0_CR

#define REG_S0_CR (0x0801)

Socket 0 command.

Definition at line 99 of file w5500_regs.h.

◆ REG_S0_DHAR0

#define REG_S0_DHAR0 (0x0806)

Socket 0 destination hardware address 0.

Definition at line 104 of file w5500_regs.h.

◆ REG_S0_DHAR1

#define REG_S0_DHAR1 (0x0807)

Socket 0 destination hardware address 1.

Definition at line 105 of file w5500_regs.h.

◆ REG_S0_DHAR2

#define REG_S0_DHAR2 (0x0808)

Socket 0 destination hardware address 2.

Definition at line 106 of file w5500_regs.h.

◆ REG_S0_DHAR3

#define REG_S0_DHAR3 (0x0809)

Socket 0 destination hardware address 3.

Definition at line 107 of file w5500_regs.h.

◆ REG_S0_DHAR4

#define REG_S0_DHAR4 (0x080a)

Socket 0 destination hardware address 4.

Definition at line 108 of file w5500_regs.h.

◆ REG_S0_DHAR5

#define REG_S0_DHAR5 (0x080b)

Socket 0 destination hardware address 5.

Definition at line 109 of file w5500_regs.h.

◆ REG_S0_DIPR0

#define REG_S0_DIPR0 (0x080c)

Socket 0 destination IP address 0.

Definition at line 110 of file w5500_regs.h.

◆ REG_S0_DIPR1

#define REG_S0_DIPR1 (0x080d)

Socket 0 destination IP address 1.

Definition at line 111 of file w5500_regs.h.

◆ REG_S0_DIPR2

#define REG_S0_DIPR2 (0x080e)

Socket 0 destination IP address 2.

Definition at line 112 of file w5500_regs.h.

◆ REG_S0_DIPR3

#define REG_S0_DIPR3 (0x080f)

Socket 0 destination IP address 3.

Definition at line 113 of file w5500_regs.h.

◆ REG_S0_DPORT0

#define REG_S0_DPORT0 (0x0810)

Socket 0 destination port 0.

Definition at line 114 of file w5500_regs.h.

◆ REG_S0_DPORT1

#define REG_S0_DPORT1 (0x0811)

Socket 0 destination port 1.

Definition at line 115 of file w5500_regs.h.

◆ REG_S0_FRAG0

#define REG_S0_FRAG0 (0x082d)

Socket 0 fragment offset in IP header 0.

Definition at line 135 of file w5500_regs.h.

◆ REG_S0_FRAG1

#define REG_S0_FRAG1 (0x082e)

Socket 0 fragment offset in IP header 1.

Definition at line 136 of file w5500_regs.h.

◆ REG_S0_IMR

#define REG_S0_IMR (0x082c)

Socket 0 interrupt mask.

Definition at line 134 of file w5500_regs.h.

◆ REG_S0_IR

#define REG_S0_IR (0x0802)

Socket 0 interrupt.

Definition at line 100 of file w5500_regs.h.

◆ REG_S0_KPALVTR

#define REG_S0_KPALVTR (0x082f)

Socket 0 keep alive timer.

Definition at line 137 of file w5500_regs.h.

◆ REG_S0_MR

#define REG_S0_MR (0x0800)

Socket 0 mode.

Definition at line 98 of file w5500_regs.h.

◆ REG_S0_MSSR0

#define REG_S0_MSSR0 (0x0812)

Socket 0 maximum segment size 0.

Definition at line 116 of file w5500_regs.h.

◆ REG_S0_MSSR1

#define REG_S0_MSSR1 (0x0813)

Socket 0 maximum segment size 1.

Definition at line 117 of file w5500_regs.h.

◆ REG_S0_PORT0

#define REG_S0_PORT0 (0x0804)

Socket 0 Source port 0.

Definition at line 102 of file w5500_regs.h.

◆ REG_S0_PORT1

#define REG_S0_PORT1 (0x0805)

Socket 0 Source port 1.

Definition at line 103 of file w5500_regs.h.

◆ REG_S0_RX_RD0

#define REG_S0_RX_RD0 (0x0828)

Socket 0 rx read pointer 0.

Definition at line 130 of file w5500_regs.h.

◆ REG_S0_RX_RD1

#define REG_S0_RX_RD1 (0x0829)

Socket 0 rx read pointer 1.

Definition at line 131 of file w5500_regs.h.

◆ REG_S0_RX_RSR0

#define REG_S0_RX_RSR0 (0x0826)

Socket 0 rx received size 0.

Definition at line 128 of file w5500_regs.h.

◆ REG_S0_RX_RSR1

#define REG_S0_RX_RSR1 (0x0827)

Socket 0 rx received size 1.

Definition at line 129 of file w5500_regs.h.

◆ REG_S0_RX_WR0

#define REG_S0_RX_WR0 (0x082a)

Socket 0 rx write pointer 0.

Definition at line 132 of file w5500_regs.h.

◆ REG_S0_RX_WR1

#define REG_S0_RX_WR1 (0x082b)

Socket 0 rx write pointer 1.

Definition at line 133 of file w5500_regs.h.

◆ REG_S0_RXBUF_SIZE

#define REG_S0_RXBUF_SIZE (0x081e)

Socket 0 receive buffer size.

Definition at line 120 of file w5500_regs.h.

◆ REG_S0_SR

#define REG_S0_SR (0x0803)

Socket 0 status.

Definition at line 101 of file w5500_regs.h.

◆ REG_S0_TOS

#define REG_S0_TOS (0x0815)

Socket 0 IP TOS.

Definition at line 118 of file w5500_regs.h.

◆ REG_S0_TTL

#define REG_S0_TTL (0x0816)

Socket 0 IP TTL.

Definition at line 119 of file w5500_regs.h.

◆ REG_S0_TX_FSR0

#define REG_S0_TX_FSR0 (0x0820)

Socket 0 tx free size 0.

Definition at line 122 of file w5500_regs.h.

◆ REG_S0_TX_FSR1

#define REG_S0_TX_FSR1 (0x0821)

Socket 0 tx free size 1.

Definition at line 123 of file w5500_regs.h.

◆ REG_S0_TX_RD0

#define REG_S0_TX_RD0 (0x0822)

Socket 0 tx read pointer 0.

Definition at line 124 of file w5500_regs.h.

◆ REG_S0_TX_RD1

#define REG_S0_TX_RD1 (0x0823)

Socket 0 tx read pointer 1.

Definition at line 125 of file w5500_regs.h.

◆ REG_S0_TX_WR0

#define REG_S0_TX_WR0 (0x0824)

Socket 0 tx write pointer 0.

Definition at line 126 of file w5500_regs.h.

◆ REG_S0_TX_WR1

#define REG_S0_TX_WR1 (0x0825)

Socket 0 tx write pointer 1.

Definition at line 127 of file w5500_regs.h.

◆ REG_S0_TXBUF_SIZE

#define REG_S0_TXBUF_SIZE (0x081f)

Socket 0 transmit buffer size.

Definition at line 121 of file w5500_regs.h.

◆ REG_SHAR0

#define REG_SHAR0 (0x0009)

Source hardware address 0.

Definition at line 53 of file w5500_regs.h.

◆ REG_SHAR1

#define REG_SHAR1 (0x000a)

Source hardware address 1.

Definition at line 54 of file w5500_regs.h.

◆ REG_SHAR2

#define REG_SHAR2 (0x000b)

Source hardware address 2.

Definition at line 55 of file w5500_regs.h.

◆ REG_SHAR3

#define REG_SHAR3 (0x000c)

Source hardware address 3.

Definition at line 56 of file w5500_regs.h.

◆ REG_SHAR4

#define REG_SHAR4 (0x000d)

Source hardware address 4.

Definition at line 57 of file w5500_regs.h.

◆ REG_SHAR5

#define REG_SHAR5 (0x000e)

Source hardware address 5.

Definition at line 58 of file w5500_regs.h.

◆ REG_SIMR

#define REG_SIMR (0x0018)

Socket interrupt mask.

Definition at line 68 of file w5500_regs.h.

◆ REG_SIPR0

#define REG_SIPR0 (0x000f)

Source IP address 0.

Definition at line 59 of file w5500_regs.h.

◆ REG_SIPR1

#define REG_SIPR1 (0x0010)

Source IP address 1.

Definition at line 60 of file w5500_regs.h.

◆ REG_SIPR2

#define REG_SIPR2 (0x0011)

Source IP address 2.

Definition at line 61 of file w5500_regs.h.

◆ REG_SIPR3

#define REG_SIPR3 (0x0012)

Source IP address 3.

Definition at line 62 of file w5500_regs.h.

◆ REG_SIR

#define REG_SIR (0x0017)

Socket interrupt.

Definition at line 67 of file w5500_regs.h.

◆ REG_SUBR0

#define REG_SUBR0 (0x0005)

Subnet mask 0.

Definition at line 49 of file w5500_regs.h.

◆ REG_SUBR1

#define REG_SUBR1 (0x0006)

Subnet mask 1.

Definition at line 50 of file w5500_regs.h.

◆ REG_SUBR2

#define REG_SUBR2 (0x0007)

Subnet mask 2.

Definition at line 51 of file w5500_regs.h.

◆ REG_SUBR3

#define REG_SUBR3 (0x0008)

Subnet mask 3.

Definition at line 52 of file w5500_regs.h.

◆ REG_UIPR0

#define REG_UIPR0 (0x0028)

Unreachable IP address 0.

Definition at line 84 of file w5500_regs.h.

◆ REG_UIPR1

#define REG_UIPR1 (0x0029)

Unreachable IP address 1.

Definition at line 85 of file w5500_regs.h.

◆ REG_UIPR2

#define REG_UIPR2 (0x002a)

Unreachable IP address 2.

Definition at line 86 of file w5500_regs.h.

◆ REG_UIPR3

#define REG_UIPR3 (0x002b)

Unreachable IP address 3.

Definition at line 87 of file w5500_regs.h.

◆ REG_UPORT0

#define REG_UPORT0 (0x002c)

Unreachable port 0.

Definition at line 88 of file w5500_regs.h.

◆ REG_UPORT1

#define REG_UPORT1 (0x002d)

Unreachable port 1.

Definition at line 89 of file w5500_regs.h.

◆ REG_VERSIONR

#define REG_VERSIONR (0x0039)

Chip version.

Definition at line 91 of file w5500_regs.h.

◆ Sn_RXBUF_SIZE_BASE

#define Sn_RXBUF_SIZE_BASE (0x001E)

Register to configure a sockets RX buffer size.

Definition at line 140 of file w5500_regs.h.

◆ Sn_TXBUF_SIZE_BASE

#define Sn_TXBUF_SIZE_BASE (0x001F)

Register to configure a sockets TX buffer size.

Definition at line 141 of file w5500_regs.h.

◆ SOCKET0_RX_BUFFER

#define SOCKET0_RX_BUFFER (0x18)

BSB for Socket 0 Receive Buffer.

Definition at line 168 of file w5500_regs.h.

◆ SOCKET0_TX_BUFFER

#define SOCKET0_TX_BUFFER (0x10)

BSB for Socket 0 Transmit Buffer.

Definition at line 169 of file w5500_regs.h.

◆ SPI_CONF

#define SPI_CONF SPI_MODE_0

Configure SPI MODE 0.

Definition at line 151 of file w5500_regs.h.