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periph_cpu.h
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1/*
2 * Copyright (C) 2016 Freie Universität Berlin
3 * 2017 OTA keys S.A.
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CPU_H
22#define PERIPH_CPU_H
23
24#include <limits.h>
25
26#include "cpu.h"
27#include "macros/units.h"
28
29#if defined(CPU_FAM_STM32F0)
31#elif defined(CPU_FAM_STM32F1)
33#elif defined(CPU_FAM_STM32F2)
35#elif defined(CPU_FAM_STM32F3)
37#elif defined(CPU_FAM_STM32F4)
39#elif defined(CPU_FAM_STM32F7)
41#elif defined(CPU_FAM_STM32G0)
43#elif defined(CPU_FAM_STM32C0)
45#elif defined(CPU_FAM_STM32G4)
47#elif defined(CPU_FAM_STM32L0)
49#elif defined(CPU_FAM_STM32L1)
51#elif defined(CPU_FAM_STM32L4)
53#elif defined(CPU_FAM_STM32L5)
55#elif defined(CPU_FAM_STM32U5)
57#elif defined(CPU_FAM_STM32WB)
59#elif defined(CPU_FAM_STM32WL)
61#endif
62
64#include "periph/cpu_common.h"
65#include "periph/cpu_dma.h"
66#include "periph/cpu_eth.h"
67#include "periph/cpu_fmc.h"
68#include "periph/cpu_gpio.h"
69#include "periph/cpu_gpio_ll.h"
70#include "periph/cpu_i2c.h"
71#include "periph/cpu_ltdc.h"
72#include "periph/cpu_pm.h"
73#include "periph/cpu_pwm.h"
74#include "periph/cpu_qdec.h"
75#include "periph/cpu_sdmmc.h"
76#include "periph/cpu_spi.h"
77#include "periph/cpu_timer.h"
78#include "periph/cpu_uart.h"
79#include "periph/cpu_usbdev.h"
80#include "periph/cpu_vbat.h"
81#include "periph/cpu_wdt.h"
82
83#ifdef MODULE_PERIPH_CAN
84#ifdef MODULE_FDCAN
85#include "fdcandev_stm32.h"
86#else
87#include "candev_stm32.h"
88#endif
89#endif
90
91#ifdef __cplusplus
92extern "C" {
93#endif
94
98typedef struct {
99 gpio_t pin;
100#if !defined(CPU_FAM_STM32F0) && !defined(CPU_FAM_STM32L0) && \
101 !defined(CPU_FAM_STM32L1) && !defined(CPU_FAM_STM32WL)
102 uint8_t dev;
103#endif
104 uint8_t chan;
105} adc_conf_t;
106
110typedef struct {
111 gpio_t pin;
112 uint8_t chan;
113} dac_conf_t;
114
119#define HAVE_PTP_CLOCK_READ 1
120#define HAVE_PTP_CLOCK_SET 1
121#define HAVE_PTP_TIMER_SET_ABSOLUTE 1
124#if !DOXYGEN /* hide implementation details */
129/* Detect the IP version based on the available register define */
130#if defined(USB_OTG_GCCFG_NOVBUSSENS)
131#define STM32_USB_OTG_CID_1x
132#elif defined(USB_OTG_GCCFG_VBDEN)
133#define STM32_USB_OTG_CID_2x
134#elif defined(USB)
135#define STM32_USB_FS_CID_1x
136#endif
137
142#if defined(USB_OTG_FS_MAX_IN_ENDPOINTS)
143#define STM32_USB_OTG_FS_NUM_EP (USB_OTG_FS_MAX_IN_ENDPOINTS)
144#elif defined(STM32_USB_OTG_CID_1x)
145#define STM32_USB_OTG_FS_NUM_EP (4)
146#elif defined(STM32_USB_OTG_CID_2x)
147#define STM32_USB_OTG_FS_NUM_EP (6)
148#endif
149
154#if defined(USB_OTG_HS_MAX_IN_ENDPOINTS)
155#define STM32_USB_OTG_HS_NUM_EP (USB_OTG_HS_MAX_IN_ENDPOINTS)
156#elif defined(STM32_USB_OTG_CID_1x)
157#define STM32_USB_OTG_HS_NUM_EP (6)
158#elif defined(STM32_USB_OTG_CID_2x)
159#define STM32_USB_OTG_HS_NUM_EP (9)
160#endif
161
172#if defined(MODULE_PERIPH_USBDEV_HS) && defined(STM32_USB_OTG_HS_NUM_EP)
173#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_HS_NUM_EP
174#elif defined(STM32_USB_OTG_FS_NUM_EP)
175#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_FS_NUM_EP
176#else
177#define USBDEV_NUM_ENDPOINTS 8
178#endif
179
180/* unify names across STM32 families */
181#ifdef SPI_CR1_CPHA_Msk
182# define STM32_SPI_CPHA_Msk SPI_CR1_CPHA_Msk
183#endif
184#ifdef SPI_CFG2_CPHA_Msk
185# define STM32_SPI_CPHA_Msk SPI_CFG2_CPHA_Msk
186#endif
187#ifdef SPI_CR1_CPOL_Msk
188# define STM32_SPI_CPOL_Msk SPI_CR1_CPOL_Msk
189#endif
190#ifdef SPI_CFG2_CPOL_Msk
191# define STM32_SPI_CPOL_Msk SPI_CFG2_CPOL_Msk
192#endif
193
201#define HAVE_SPI_MODE_T
202typedef enum {
203 SPI_MODE_0 = 0,
204 SPI_MODE_1 = STM32_SPI_CPHA_Msk,
205 SPI_MODE_2 = STM32_SPI_CPOL_Msk,
206 SPI_MODE_3 = STM32_SPI_CPOL_Msk | STM32_SPI_CPHA_Msk,
207} spi_mode_t;
210#endif /* !DOXYGEN */
211
212#ifdef __cplusplus
213}
214#endif
215
216#endif /* PERIPH_CPU_H */
bxCAN specific definitions
gpio_t adc_conf_t
ADC configuration wrapper.
Definition periph_cpu.h:337
Backup SRAM CPU specific definitions for the STM32 family.
DMA CPU specific definitions for the STM32 family.
Ethernet CPU specific definitions for the STM32 family.
Specific FMC definitions for the STM32.
GPIO CPU definitions for the STM32 family.
GPIO LL CPU definitions for the STM32 family.
I2C CPU specific definitions for the STM32 family.
LTDC CPU specific definitions for the STM32 family.
PWM CPU specific definitions for the STM32 family.
QDEC CPU specific definitions for the STM32 family.
CPU specific definitions for SDIO/SDMMC for the STM32 family.
SPI CPU specific definitions for the STM32 family.
Timer CPU specific definitions for the STM32 family.
UART CPU specific definitions for the STM32 family.
USB CPU specific definitions for the STM32 family.
CPU internal VBAT interface and definitions of the STM32 family.
Watchdog CPU definitions for the STM32 family.
FDCAN specific definitions.
uint16_t gpio_t
GPIO type identifier.
Definition periph_cpu.h:117
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
STM32C0 CPU specific definitions for internal peripheral handling.
Common CPU definitions for the STM32 family.
Power Management (PM) CPU specific definitions for the STM32 family.
STM32F0 CPU specific definitions for internal peripheral handling.
STM32F1 CPU specific definitions for internal peripheral handling.
STM32F2 CPU specific definitions for internal peripheral handling.
STM32F3 CPU specific definitions for internal peripheral handling.
STM32F4 CPU specific definitions for internal peripheral handling.
STM32F7 CPU specific definitions for internal peripheral handling.
STM32G0 CPU specific definitions for internal peripheral handling.
STM3G4 CPU specific definitions for internal peripheral handling.
STM32L0 CPU specific definitions for internal peripheral handling.
STM32L1 CPU specific definitions for internal peripheral handling.
STM32L4 CPU specific definitions for internal peripheral handling.
STM32L5 CPU specific definitions for internal peripheral handling.
STM32U5 CPU specific definitions for internal peripheral handling.
STM32WB CPU specific definitions for internal peripheral handling.
STM32WL CPU specific definitions for internal peripheral handling.
DAC line configuration data.
Definition periph_cpu.h:301
Unit helper macros.