29#if defined(CPU_FAM_STM32F0)
31#elif defined(CPU_FAM_STM32F1)
33#elif defined(CPU_FAM_STM32F2)
35#elif defined(CPU_FAM_STM32F3)
37#elif defined(CPU_FAM_STM32F4)
39#elif defined(CPU_FAM_STM32F7)
41#elif defined(CPU_FAM_STM32G0)
43#elif defined(CPU_FAM_STM32C0)
45#elif defined(CPU_FAM_STM32G4)
47#elif defined(CPU_FAM_STM32L0)
49#elif defined(CPU_FAM_STM32L1)
51#elif defined(CPU_FAM_STM32L4)
53#elif defined(CPU_FAM_STM32L5)
55#elif defined(CPU_FAM_STM32U5)
57#elif defined(CPU_FAM_STM32WB)
59#elif defined(CPU_FAM_STM32WL)
83#ifdef MODULE_PERIPH_CAN
100#if !defined(CPU_FAM_STM32F0) && !defined(CPU_FAM_STM32L0) && \
101 !defined(CPU_FAM_STM32L1) && !defined(CPU_FAM_STM32WL)
119#define HAVE_PTP_CLOCK_READ 1
120#define HAVE_PTP_CLOCK_SET 1
121#define HAVE_PTP_TIMER_SET_ABSOLUTE 1
130#if defined(USB_OTG_GCCFG_NOVBUSSENS)
131#define STM32_USB_OTG_CID_1x
132#elif defined(USB_OTG_GCCFG_VBDEN)
133#define STM32_USB_OTG_CID_2x
135#define STM32_USB_FS_CID_1x
142#if defined(USB_OTG_FS_MAX_IN_ENDPOINTS)
143#define STM32_USB_OTG_FS_NUM_EP (USB_OTG_FS_MAX_IN_ENDPOINTS)
144#elif defined(STM32_USB_OTG_CID_1x)
145#define STM32_USB_OTG_FS_NUM_EP (4)
146#elif defined(STM32_USB_OTG_CID_2x)
147#define STM32_USB_OTG_FS_NUM_EP (6)
154#if defined(USB_OTG_HS_MAX_IN_ENDPOINTS)
155#define STM32_USB_OTG_HS_NUM_EP (USB_OTG_HS_MAX_IN_ENDPOINTS)
156#elif defined(STM32_USB_OTG_CID_1x)
157#define STM32_USB_OTG_HS_NUM_EP (6)
158#elif defined(STM32_USB_OTG_CID_2x)
159#define STM32_USB_OTG_HS_NUM_EP (9)
172#if defined(MODULE_PERIPH_USBDEV_HS) && defined(STM32_USB_OTG_HS_NUM_EP)
173#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_HS_NUM_EP
174#elif defined(STM32_USB_OTG_FS_NUM_EP)
175#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_FS_NUM_EP
177#define USBDEV_NUM_ENDPOINTS 8
181#ifdef SPI_CR1_CPHA_Msk
182# define STM32_SPI_CPHA_Msk SPI_CR1_CPHA_Msk
184#ifdef SPI_CFG2_CPHA_Msk
185# define STM32_SPI_CPHA_Msk SPI_CFG2_CPHA_Msk
187#ifdef SPI_CR1_CPOL_Msk
188# define STM32_SPI_CPOL_Msk SPI_CR1_CPOL_Msk
190#ifdef SPI_CFG2_CPOL_Msk
191# define STM32_SPI_CPOL_Msk SPI_CFG2_CPOL_Msk
201#define HAVE_SPI_MODE_T
206 SPI_MODE_3 = STM32_SPI_CPOL_Msk | STM32_SPI_CPHA_Msk,
bxCAN specific definitions
gpio_t adc_conf_t
ADC configuration wrapper.
Backup SRAM CPU specific definitions for the STM32 family.
DMA CPU specific definitions for the STM32 family.
Ethernet CPU specific definitions for the STM32 family.
Specific FMC definitions for the STM32.
GPIO CPU definitions for the STM32 family.
GPIO LL CPU definitions for the STM32 family.
I2C CPU specific definitions for the STM32 family.
LTDC CPU specific definitions for the STM32 family.
PWM CPU specific definitions for the STM32 family.
QDEC CPU specific definitions for the STM32 family.
CPU specific definitions for SDIO/SDMMC for the STM32 family.
SPI CPU specific definitions for the STM32 family.
Timer CPU specific definitions for the STM32 family.
UART CPU specific definitions for the STM32 family.
USB CPU specific definitions for the STM32 family.
CPU internal VBAT interface and definitions of the STM32 family.
Watchdog CPU definitions for the STM32 family.
FDCAN specific definitions.
uint16_t gpio_t
GPIO type identifier.
spi_mode_t
Support SPI modes.
@ SPI_MODE_0
CPOL=0, CPHA=0.
@ SPI_MODE_2
CPOL=1, CPHA=0.
@ SPI_MODE_1
CPOL=0, CPHA=1.
@ SPI_MODE_3
CPOL=1, CPHA=1.
STM32C0 CPU specific definitions for internal peripheral handling.
Common CPU definitions for the STM32 family.
Power Management (PM) CPU specific definitions for the STM32 family.
STM32F0 CPU specific definitions for internal peripheral handling.
STM32F1 CPU specific definitions for internal peripheral handling.
STM32F2 CPU specific definitions for internal peripheral handling.
STM32F3 CPU specific definitions for internal peripheral handling.
STM32F4 CPU specific definitions for internal peripheral handling.
STM32F7 CPU specific definitions for internal peripheral handling.
STM32G0 CPU specific definitions for internal peripheral handling.
STM3G4 CPU specific definitions for internal peripheral handling.
STM32L0 CPU specific definitions for internal peripheral handling.
STM32L1 CPU specific definitions for internal peripheral handling.
STM32L4 CPU specific definitions for internal peripheral handling.
STM32L5 CPU specific definitions for internal peripheral handling.
STM32U5 CPU specific definitions for internal peripheral handling.
STM32WB CPU specific definitions for internal peripheral handling.
STM32WL CPU specific definitions for internal peripheral handling.
DAC line configuration data.