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periph_conf.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2020 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef PERIPH_CONF_H
21#define PERIPH_CONF_H
22
23#include "periph_cpu.h"
24#include "cfg_clock_32_1.h"
25#include "cfg_rtt_default.h"
26#include "cfg_timer_default.h"
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
36static const uart_conf_t uart_config[] = {
37 {
38 .dev = NRF_UARTE0,
39 .rx_pin = GPIO_PIN(1, 10),
40 .tx_pin = GPIO_PIN(1, 3),
41#ifdef MODULE_PERIPH_UART_HW_FC
42 .rts_pin = GPIO_UNDEF,
43 .cts_pin = GPIO_UNDEF,
44#endif
45 .irqn = UARTE0_UART0_IRQn,
46 },
47};
48
49#define UART_0_ISR (isr_uart0)
50
51#define UART_NUMOF ARRAY_SIZE(uart_config)
58static const i2c_conf_t i2c_config[] = {
59 {
60 .dev = NRF_TWIM0,
61 .scl = GPIO_PIN(0, 2),
62 .sda = GPIO_PIN(0, 31),
63 .speed = I2C_SPEED_NORMAL
64 },
65};
66
67#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
74static const spi_conf_t spi_config[] = {
75 {
76 .dev = NRF_SPIM0,
77 .sclk = GPIO_PIN(0, 13),
78 .mosi = GPIO_PIN(1, 1),
79 .miso = GPIO_PIN(1, 8),
80 }
81};
82
83#define SPI_NUMOF ARRAY_SIZE(spi_config)
86#ifdef __cplusplus
87}
88#endif
89
90#endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
Common clock configuration for the nRF52 based boards.
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219