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periph_cpu_common.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2015 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CPU_COMMON_H
20#define PERIPH_CPU_COMMON_H
21
22#include <stdbool.h>
23
24#include "bitarithm.h"
25#include "compiler_hints.h"
26#include "cpu.h"
27#include "msp430_regs.h"
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
37#define HAVE_GPIO_T
38typedef uint16_t gpio_t;
44#define GPIO_UNDEF (0xffff)
45
49#define GPIO_PIN(x, y) ((gpio_t)(((x & 0xff) << 8) | (1 << (y & 0x07))))
50
54#define SPI_HWCS(x) (SPI_CS_UNDEF)
55
65#define TIMER_CHANNEL_NUMOF 7
66
70#define RAMSTART 0x200
71
76#define HAVE_GPIO_FLANK_T
80typedef enum {
81 GPIO_FALLING = 0xff,
82 GPIO_RISING = 0x00,
83 GPIO_BOTH = 0xab
90enum {
91 P1 = 1,
92 P2 = 2,
93 P3 = 3,
94 P4 = 4,
95 P5 = 5,
96 P6 = 6,
97};
98
99#ifndef DOXYGEN
100#define HAVE_GPIO_STATE_T
101typedef enum {
109
110#define HAVE_GPIO_SLEW_T
111typedef enum {
113 GPIO_SLEW_SLOW = 0,
114 GPIO_SLEW_FAST = 0,
117
118#define HAVE_GPIO_PULL_STRENGTH_T
119typedef enum {
121 GPIO_PULL_WEAK = 0,
125
126#define HAVE_GPIO_DRIVE_STRENGTH_T
127typedef enum {
129 GPIO_DRIVE_WEAK = 0,
133#endif /* !DOXYGEN */
134
141void gpio_periph_mode(gpio_t pin, bool enable);
142
149extern uint32_t msp430_dco_freq;
150
173
202
224
246
268
344
354
365
369typedef struct {
380
412
417
426
435
458
468void clock_init(void);
469
476
483
494
505
506#ifdef __cplusplus
507}
508#endif
509
510#endif /* PERIPH_CPU_COMMON_H */
gpio_flank_t
Definition periph_cpu.h:180
Helper functions for bit arithmetic.
Common macros and compiler attributes/pragmas configuration.
#define PURE
The function has no effects except the return value and its return value depends only on the paramete...
gpio_pull_strength_t
Enumeration of pull resistor values.
Definition gpio_ll.h:268
gpio_state_t
Enumeration of GPIO states (direction)
Definition gpio_ll.h:158
gpio_slew_t
Enumeration of slew rate settings.
Definition gpio_ll.h:332
gpio_drive_strength_t
Enumeration of drive strength options.
Definition gpio_ll.h:299
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
Definition gpio_ll.h:269
@ GPIO_PULL_WEAK
Use a weak pull resistor.
Definition gpio_ll.h:270
@ GPIO_PULL_STRONG
Use a strong pull resistor.
Definition gpio_ll.h:271
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
Definition gpio_ll.h:272
@ GPIO_OUTPUT_OPEN_SOURCE
Use pin as output in open emitter configuration.
Definition gpio_ll.h:195
@ GPIO_USED_BY_PERIPHERAL
The GPIO pin is used by a peripheral.
Definition gpio_ll.h:214
@ GPIO_OUTPUT_OPEN_DRAIN
Use pin as output in open collector configuration.
Definition gpio_ll.h:182
@ GPIO_OUTPUT_PUSH_PULL
Use pin as output in push-pull configuration.
Definition gpio_ll.h:169
@ GPIO_DISCONNECT
Disconnect pin from all peripherals.
Definition gpio_ll.h:242
@ GPIO_INPUT
Use pin as input.
Definition gpio_ll.h:201
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
Definition gpio_ll.h:333
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
Definition gpio_ll.h:336
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
Definition gpio_ll.h:335
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
Definition gpio_ll.h:337
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
Definition gpio_ll.h:302
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
Definition gpio_ll.h:301
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
Definition gpio_ll.h:303
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
Definition gpio_ll.h:300
msp430_port_p3_p6_t PORT_5
Register map of GPIO PORT 5.
msp430_timer_t TIMER_A
Register map of the timer A control registers.
msp430_clock_t
IDs of the different clock domains on the MSP430.
@ MSP430_CLOCK_AUXILIARY
Auxiliary clock.
@ MSP430_CLOCK_NUMOF
Number of clock domains.
@ MSP430_CLOCK_SUBMAIN
Subsystem main clock.
msp430_main_clock_source_t
Possible clock sources to generate the main clock from.
@ MAIN_CLOCK_SOURCE_XT2CLK
High frequency crystal between 450 kHz and 8 MHz.
@ MAIN_CLOCK_SOURCE_DCOCLK
Internal digitally controlled oscillator (DCO) with RC-type characteristics.
@ MAIN_CLOCK_SOURCE_LFXT1CLK
Low frequency 32.768 kHz or high frequency crystal between 450 kHz and 8 MHz.
uint32_t PURE msp430_submain_clock_freq(void)
Get the configured submain clock frequency.
msp430_timer_t TIMER_B
Register map of the timer B control registers.
msp430_port_p1_p2_t PORT_2
Register map of GPIO PORT 2.
void clock_init(void)
Call during boot up process to initialize the clock.
msp430_port_p1_p2_t PORT_1
Register map of GPIO PORT 1.
msp430_submain_clock_source_t
Possible clock sources to generate the submain clock from.
@ SUBMAIN_CLOCK_SOURCE_LFXT1CLK
Low frequency 32.768 kHz or high frequency crystal between 450 kHz and 8 MHz.
@ SUBMAIN_CLOCK_SOURCE_DCOCLK
Internal digitally controlled oscillator (DCO) with RC-type characteristics.
@ SUBMAIN_CLOCK_SOURCE_XT2CLK
High frequency crystal between 450 kHz and 8 MHz.
msp430_port_p3_p6_t PORT_6
Register map of GPIO PORT 6.
REG16 TIMER_B_IRQFLAGS
IRQ flags for TIMER_B.
void msp430_clock_release(msp430_clock_t clock)
Decrease the refcount of the subsystem main clock.
REG16 TIMER_A_IRQFLAGS
IRQ flags for TIMER_A.
msp430_submain_clock_divider_t
Clock dividers for the submain clock.
@ SUBMAIN_CLOCK_DIVIDE_BY_2
Divide the main clock by 2.
@ SUBMAIN_CLOCK_DIVIDE_BY_8
Divide the main clock by 8.
@ SUBMAIN_CLOCK_DIVIDE_BY_1
Divide the main clock by 1.
@ SUBMAIN_CLOCK_DIVIDE_BY_4
Divide the main clock by 4.
msp430_auxiliary_clock_divider_t
Clock dividers for the auxiliary clock.
@ AUXILIARY_CLOCK_DIVIDE_BY_4
Divide the main clock by 4.
@ AUXILIARY_CLOCK_DIVIDE_BY_1
Divide the main clock by 1.
@ AUXILIARY_CLOCK_DIVIDE_BY_2
Divide the main clock by 2.
@ AUXILIARY_CLOCK_DIVIDE_BY_8
Divide the main clock by 8.
uint32_t PURE msp430_auxiliary_clock_freq(void)
Get the configured auxiliary clock frequency.
msp430_port_p3_p6_t PORT_4
Register map of GPIO PORT 4.
msp430_timer_clock_source_t
Enumeration of possible clock sources for a timer.
@ TIMER_CLOCK_SOURCE_AUXILIARY_CLOCK
Auxiliary clock as clock source.
@ TIMER_CLOCK_SOURCE_TXCLK
External TxCLK as clock source.
@ TIMER_CLOCK_SOURCE_SUBMAIN_CLOCK
Sub-system master clock as clock source.
@ TIMER_CLOCK_SOURCE_INCLK
External INCLK as clock source.
void msp430_clock_acquire(msp430_clock_t clock)
Increase the refcount of the given clock.
msp430_main_clock_divider_t
Clock dividers for the main clock.
@ MAIN_CLOCK_DIVIDE_BY_1
Divide the main clock by 1.
@ MAIN_CLOCK_DIVIDE_BY_8
Divide the main clock by 8.
@ MAIN_CLOCK_DIVIDE_BY_2
Divide the main clock by 2.
@ MAIN_CLOCK_DIVIDE_BY_4
Divide the main clock by 4.
uint32_t msp430_dco_freq
The measured DCO frequency.
void default_clock_init(void)
Initialize the basic clock system to provide the main clock, the subsystem clock, and the auxiliary c...
@ P6
PORT 6.
@ P1
PORT 1.
@ P4
PORT 4.
@ P3
PORT 3.
@ P2
PORT 2.
@ P5
PORT 5.
msp430_port_p3_p6_t PORT_3
Register map of GPIO PORT 3.
void gpio_periph_mode(gpio_t pin, bool enable)
Enable or disable a pin to be used by peripheral modules.
#define TXSSEL_SMCLK
Sub-system master clock as clock source.
#define TXSSEL_TXCLK
External TxCLK as clock source.
#define TXSSEL_ACLK
Auxiliary clock as clock source.
#define TXSSEL_INCLK
External INCLK as clock source.
#define REG16(ADDR)
Type for 16-bit registers.
Definition periph_gba.h:37
MSP430Fxzy Basic Clock System Parameters.
msp430_main_clock_source_t main_clock_source
The clock source to select for the main clock.
uint32_t lfxt1_frequency
The frequency of the LFXT1 crystal in Hz.
msp430_auxiliary_clock_divider_t auxiliary_clock_divier
Divider of the auxiliary clock.
uint32_t xt2_frequency
The frequency of the XT2 crystal in Hz.
msp430_submain_clock_source_t submain_clock_source
The clock source to select for the submain CPU clock.
uint32_t target_dco_frequency
The target frequency to run the DCO at in Hz.
msp430_submain_clock_divider_t submain_clock_divier
Divider of the submain clock.
bool has_xt2
A high frequency crystal (e.g.
msp430_main_clock_divider_t main_clock_divier
Divider of the main clock.
bool has_r_osc
An external resistor connected to source the current for the DCO.
GPIO Port 1/2 (with interrupt functionality)
Definition msp430_regs.h:63
GPIO Port 3..6 (without interrupt functionality)
Timer peripheral registers.
Timer device configuration.
Definition periph_cpu.h:264
msp430_timer_t * timer
Hardware timer to use.
REG16 * irq_flags
"Timer interrupt vector" register
msp430_timer_clock_source_t clock_source
Clock source to use.