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msp430_regs.h
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1/*
2 * Copyright (C) 2015 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
23#ifndef F2XX_G2XX_MSP430_REGS_H
24#define F2XX_G2XX_MSP430_REGS_H
25
26#include <stdint.h>
27#include <stddef.h>
28
29#include "msp430_regs_common.h"
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
44#define MSP430_USCI_A_B_OFFSET 3U
45
57#define MSP430_USCI_B_FROM_USCI_A(usci_a) \
58 ((msp430_usci_b_t *)((uintptr_t)(usci_a) + MSP430_USCI_A_B_OFFSET))
59
71
75typedef struct {
77 uint8_t _padding1;
79 uint8_t _padding2;
81 uint8_t _padding3;
84
101
115
124#define UCSSEL_UCLKI UCSSEL_0
125#define UCSSEL_ACLK UCSSEL_1
126#define UCSSEL_SMCLK UCSSEL_2
128#if (UCSSEL0 == 0x40) || DOXYGEN
129# define UCSSEL_Pos 6
130#else
131# error "USSEL field in USCI CTL1 register is at unexpected position"
132#endif
143#define UCBRS_MASK UCBRS_7
145#if (UCBRS_7 == 0x0E) || defined(DOXYGEN)
146# define UCBRS_Pos 1
148#else
149/* The datasheet for the whole MCU family states the field is in bits 3-1,
150 * but let's better be safe than sorry here */
151# error "UCBRS field in the UCAxMCTL register at unexpected position."
152#endif
153
171{
172 uintptr_t usci_b = (uintptr_t)usci_a + offsetof(msp430_usci_a_t, CTL0);
173 return (msp430_usci_b_t *)usci_b;
174}
175
206#ifdef __cplusplus
207}
208#endif
209
210#endif /* F2XX_G2XX_MSP430_REGS_H */
#define REG8
Register types.
msp430_usci_a_t USCI_A0
USCI_A0 register map.
msp430_usci_b_t USCI_B1
USCI_B1 register map.
msp430_usci_b_t USCI_B0
USCI_B0 register map.
static msp430_usci_b_t * msp430_usci_b_from_usci_a(msp430_usci_a_t *usci_a)
"Convert" a USCI A into an USCI B interface
msp430_usci_a_t USCI_A1
USCI_A1 register map.
Cortex CMSIS style definition of MSP430 registers.
GPIO Port 1/2 (with interrupt functionality)
Definition msp430_regs.h:63
REG8 IFG
interrupt flag
Definition msp430_regs.h:65
REG8 SEL
alternative function select
Definition msp430_regs.h:68
REG8 IES
interrupt edge select
Definition msp430_regs.h:66
REG8 REN
pull resistor enable
Definition msp430_regs.h:69
msp430_port_t base
common GPIO port registers
Definition msp430_regs.h:64
REG8 IE
interrupt enable
Definition msp430_regs.h:67
GPIO Port 7/8 (different register layout than Ports 1-6)
Definition msp430_regs.h:75
REG8 IN
input data
Definition msp430_regs.h:76
uint8_t _padding1
unrelated I/O
Definition msp430_regs.h:77
REG8 OD
output data
Definition msp430_regs.h:78
uint8_t _padding3
unrelated I/O
Definition msp430_regs.h:81
REG8 SEL
alternative function select
Definition msp430_regs.h:82
REG8 DIR
pin direction
Definition msp430_regs.h:80
uint8_t _padding2
unrelated I/O
Definition msp430_regs.h:79
Common MSP GPIO Port Registers.
Universal Serial Control Interface Type A (USCI_A) Registers.
Definition msp430_regs.h:88
REG8 MCTL
modulation control
Definition msp430_regs.h:96
REG8 IRTCTL
IrDA transmit control.
Definition msp430_regs.h:90
REG8 TXBUF
transmit buffer
Definition msp430_regs.h:99
REG8 ABCTL
auto baud rate control
Definition msp430_regs.h:89
REG8 BR1
baud rate control 1
Definition msp430_regs.h:95
REG8 BR0
baud rate control 0
Definition msp430_regs.h:94
REG8 STAT
status register
Definition msp430_regs.h:97
REG8 RXBUF
receive buffer
Definition msp430_regs.h:98
REG8 CTL1
control 1
Definition msp430_regs.h:93
REG8 IRRCTL
IrDA receive control.
Definition msp430_regs.h:91
REG8 CTL0
control 0
Definition msp430_regs.h:92
Universal Serial Control Interface Type B (USCI_B) Registers.
REG8 RXBUF
receive buffer
REG8 BR1
baud rate control 1
REG8 BR0
baud rate control 0
REG8 STAT
status register
REG8 CTL1
control 1
REG8 CTL0
control 0
REG8 TXBUF
transmit buffer
REG8 MCTL
modulation control