44#define GRETH_CTRL_TXEN (1u << 0)
45#define GRETH_CTRL_RXEN (1u << 1)
46#define GRETH_CTRL_TXIRQEN (1u << 2)
47#define GRETH_CTRL_RXIRQEN (1u << 3)
48#define GRETH_CTRL_FD (1u << 4)
49#define GRETH_CTRL_PRO (1u << 5)
50#define GRETH_CTRL_RST (1u << 6)
51#define GRETH_CTRL_SPD (1u << 7)
52#define GRETH_CTRL_GB (1u << 8)
53#define GRETH_CTRL_EDCLDIS (1u << 14)
54#define GRETH_CTRL_GBIT_CAP (1u << 27)
55#define GRETH_CTRL_EDCL_CAP (1u << 26)
64#define GRETH_STATUS_RXERR (1u << 0)
65#define GRETH_STATUS_TXERR (1u << 1)
66#define GRETH_STATUS_RXIRQ (1u << 2)
67#define GRETH_STATUS_TXIRQ (1u << 3)
68#define GRETH_STATUS_PHYIRQ (1u << 4)
75#define GRETH_MDIO_OP_WR (1u)
76#define GRETH_MDIO_OP_RD (2u)
77#define GRETH_MDIO_BUSY (1u << 3)
78#define GRETH_MDIO_NVALID (1u << 4)
79#define GRETH_MDIO_REGSHIFT (6u)
80#define GRETH_MDIO_PHYSHIFT (11u)
81#define GRETH_MDIO_DATASHIFT (16u)
91#define GRETH_BD_LEN_MASK (0x7FFu)
92#define GRETH_BD_EN (1u << 11)
93#define GRETH_BD_WR (1u << 12)
94#define GRETH_BD_IE (1u << 13)
101#define GRETH_TXBD_ERR_UE (1u << 14)
102#define GRETH_TXBD_ERR_AL (1u << 15)
103#define GRETH_TXBD_ERR_LC (1u << 16)
105#define GRETH_TXBD_ERR_MASK (GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL | \
113#define GRETH_RXBD_ERR_AE (1u << 14)
114#define GRETH_RXBD_ERR_FT (1u << 15)
115#define GRETH_RXBD_ERR_CRC (1u << 16)
116#define GRETH_RXBD_ERR_OE (1u << 17)
117#define GRETH_RXBD_ERR_LE (1u << 18)
119#define GRETH_RXBD_ERR_MASK (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_FT | \
120 GRETH_RXBD_ERR_CRC | GRETH_RXBD_ERR_OE | \
128#define GRETH_MII_CTRL (0)
129#define GRETH_MII_STATUS (1)
130#define GRETH_MII_ADV (4)
131#define GRETH_MII_LPA (5)
133#define GRETH_MII_CTRL_RST (1u << 15)
134#define GRETH_MII_CTRL_ANEG (1u << 12)
135#define GRETH_MII_CTRL_SPD100 (1u << 13)
136#define GRETH_MII_CTRL_FD (1u << 8)
137#define GRETH_MII_STATUS_ANEG_DONE (1u << 5)
138#define GRETH_MII_STATUS_LINK (1u << 2)
149#define GRETH_MII_LPA_10_HD (1u << 5)
150#define GRETH_MII_LPA_10_FD (1u << 6)
151#define GRETH_MII_LPA_100_HD (1u << 7)
152#define GRETH_MII_LPA_100_FD (1u << 8)
volatile uint32_t mac_lsb
0x0C MAC address bytes [2:5]
volatile uint32_t rx_desc
0x18 RX descriptor table base address
volatile uint32_t mac_msb
0x08 MAC address bytes [0:1]
volatile uint32_t tx_desc
0x14 TX descriptor table base address
volatile uint32_t edcl_ip
0x1C EDCL IP address (read-only)
volatile uint32_t ctrl
0x00 Control
volatile uint32_t mdio
0x10 MDIO control and data
volatile uint32_t status
0x04 Status / Interrupt flags