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periph_conf.h File Reference
#include "periph_cpu.h"
+ Include dependency graph for periph_conf.h:
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Go to the source code of this file.

Clock system configuration

#define CLOCK_CORECLOCK   (48000000ul)
 
#define CLOCK_BUSCLOCK   (CLOCK_CORECLOCK / 1)
 
static const clock_config_t clock_config
 

Timer configuration

#define PIT_NUMOF   (2U)
 
#define PIT_CONFIG
 
#define LPTMR_NUMOF   (0U)
 
#define LPTMR_CONFIG
 
#define TIMER_NUMOF   ((PIT_NUMOF) + (LPTMR_NUMOF))
 
#define PIT_BASECLOCK   (CLOCK_BUSCLOCK)
 
#define PIT_ISR_0   isr_pit1
 
#define PIT_ISR_1   isr_pit3
 

UART configuration

#define UART_0_ISR   (isr_uart0_rx_tx)
 
#define UART_1_ISR   (isr_uart1_rx_tx)
 
#define UART_NUMOF   ARRAY_SIZE(uart_config)
 
static const uart_conf_t uart_config []
 

PWM configuration

#define PWM_NUMOF   ARRAY_SIZE(pwm_config)
 
static const pwm_conf_t pwm_config []
 

Macro Definition Documentation

◆ CLOCK_BUSCLOCK

#define CLOCK_BUSCLOCK   (CLOCK_CORECLOCK / 1)

Definition at line 71 of file periph_conf.h.

◆ CLOCK_CORECLOCK

#define CLOCK_CORECLOCK   (48000000ul)

Definition at line 70 of file periph_conf.h.

◆ LPTMR_CONFIG

#define LPTMR_CONFIG
Value:
{ \
}

Definition at line 90 of file periph_conf.h.

◆ LPTMR_NUMOF

#define LPTMR_NUMOF   (0U)

Definition at line 89 of file periph_conf.h.

◆ PIT_BASECLOCK

#define PIT_BASECLOCK   (CLOCK_BUSCLOCK)

Definition at line 94 of file periph_conf.h.

◆ PIT_CONFIG

#define PIT_CONFIG
Value:
{ \
{ \
.prescaler_ch = 0, \
.count_ch = 1, \
}, \
{ \
.prescaler_ch = 2, \
.count_ch = 3, \
}, \
}

Definition at line 79 of file periph_conf.h.

◆ PIT_ISR_0

#define PIT_ISR_0   isr_pit1

Definition at line 95 of file periph_conf.h.

◆ PIT_ISR_1

#define PIT_ISR_1   isr_pit3

Definition at line 96 of file periph_conf.h.

◆ PIT_NUMOF

#define PIT_NUMOF   (2U)

Definition at line 78 of file periph_conf.h.

◆ PWM_NUMOF

#define PWM_NUMOF   ARRAY_SIZE(pwm_config)

Definition at line 167 of file periph_conf.h.

◆ TIMER_NUMOF

#define TIMER_NUMOF   ((PIT_NUMOF) + (LPTMR_NUMOF))

Definition at line 92 of file periph_conf.h.

◆ UART_0_ISR

#define UART_0_ISR   (isr_uart0_rx_tx)

Definition at line 132 of file periph_conf.h.

◆ UART_1_ISR

#define UART_1_ISR   (isr_uart1_rx_tx)

Definition at line 133 of file periph_conf.h.

◆ UART_NUMOF

#define UART_NUMOF   ARRAY_SIZE(uart_config)

Definition at line 135 of file periph_conf.h.

Variable Documentation

◆ clock_config

const clock_config_t clock_config
static
Initial value:
= {
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(1),
.rtc_clc = 0,
.osc32ksel = SIM_SOPT1_OSC32KSEL(2),
.clock_flags =
KINETIS_CLOCK_RTCOSC_EN |
KINETIS_CLOCK_USE_FAST_IRC |
0,
.default_mode = KINETIS_MCG_MODE_FEE,
.erc_range = KINETIS_MCG_ERC_RANGE_LOW,
.osc_clc = OSC_CR_SC16P_MASK,
.oscsel = MCG_C7_OSCSEL(1),
.fcrdiv = MCG_SC_FCRDIV(0),
.fll_frdiv = MCG_C1_FRDIV(0b000),
.fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464,
.fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1464,
.pll_prdiv = MCG_C5_PRDIV0(0b00111),
.pll_vdiv = MCG_C6_VDIV0(0b01100),
}

Definition at line 32 of file periph_conf.h.

◆ pwm_config

const pwm_conf_t pwm_config[]
static
Initial value:
= {
{
.ftm = FTM0,
.chan = {
{ .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
{ .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
},
.chan_numof = 2,
.ftm_num = 0
},
{
.ftm = FTM1,
.chan = {
{ .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
{ .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
},
.chan_numof = 2,
.ftm_num = 1
}
}
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.

Definition at line 142 of file periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = UART0,
.freq = CLOCK_CORECLOCK,
.pin_rx = GPIO_PIN(PORT_B, 16),
.pin_tx = GPIO_PIN(PORT_B, 17),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART0_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART0_SHIFT,
.mode = UART_MODE_8N1,
.type = KINETIS_UART,
},
{
.dev = UART1,
.freq = CLOCK_CORECLOCK,
.pin_rx = GPIO_PIN(PORT_C, 3),
.pin_tx = GPIO_PIN(PORT_C, 4),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART1_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART1_SHIFT,
.mode = UART_MODE_8N1,
.type = KINETIS_UART,
},
}
#define CLOCK_CORECLOCK
Clock configuration.
Definition periph_cpu.h:31
@ PORT_B
port B
Definition periph_cpu.h:48
#define UART0
UART0 register bank.
#define UART1
UART1 register bank.
@ KINETIS_UART
Kinetis UART module type.
Definition periph_cpu.h:538
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition periph_cpu.h:294

Definition at line 103 of file periph_conf.h.