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periph_conf.h
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1/*
2 * Copyright (C) 2020 Benjamin Valentin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22#include <stdint.h>
23
24#include "cpu.h"
25#include "periph_cpu.h"
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
62#define CLOCK_USE_PLL (1)
63
64#if CLOCK_USE_PLL
65/* edit these values to adjust the PLL output frequency */
66#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
67#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
68#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
69#else
70/* edit this value to your needs */
71#define CLOCK_DIV (1U)
72/* generate the actual core clock frequency */
73#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
74#endif
81static const tc32_conf_t timer_config[] = {
82 { /* Timer 0 - System Clock */
83 .dev = TC3,
84 .irq = TC3_IRQn,
85 .pm_mask = PM_APBCMASK_TC3,
86 .gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
87#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
88 .gclk_src = SAM0_GCLK_1MHZ,
89#else
90 .gclk_src = SAM0_GCLK_MAIN,
91#endif
92 .flags = TC_CTRLA_MODE_COUNT16,
93 },
94 { /* Timer 1 */
95 .dev = TC4,
96 .irq = TC4_IRQn,
97 .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
98 .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
99#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
100 .gclk_src = SAM0_GCLK_1MHZ,
101#else
102 .gclk_src = SAM0_GCLK_MAIN,
103#endif
104 .flags = TC_CTRLA_MODE_COUNT32,
105 }
106};
107
108#define TIMER_0_MAX_VALUE 0xffff
109
110/* interrupt function name mapping */
111#define TIMER_0_ISR isr_tc3
112#define TIMER_1_ISR isr_tc4
113
114#define TIMER_NUMOF ARRAY_SIZE(timer_config)
121static const uart_conf_t uart_config[] = {
122 {
123 .dev = &SERCOM2->USART,
124 .rx_pin = GPIO_PIN(PA, 9), /* D5 */
125 .tx_pin = GPIO_PIN(PA, 8), /* D4 */
126 .mux = GPIO_MUX_D,
127 .rx_pad = UART_PAD_RX_1,
128 .tx_pad = UART_PAD_TX_0,
129 .flags = UART_FLAG_NONE,
130 .gclk_src = SAM0_GCLK_MAIN,
131 },
132 {
133 .dev = &SERCOM0->USART,
134 .rx_pin = GPIO_PIN(PA, 5), /* D1 */
135 .tx_pin = GPIO_PIN(PA, 4), /* D0 */
136 .mux = GPIO_MUX_D,
137 .rx_pad = UART_PAD_RX_1,
138 .tx_pad = UART_PAD_TX_0,
139 .flags = UART_FLAG_NONE,
140 .gclk_src = SAM0_GCLK_MAIN,
141 }
142};
143
144/* interrupt function name mapping */
145#define UART_0_ISR isr_sercom2
146#define UART_1_ISR isr_sercom0
147
148#define UART_NUMOF ARRAY_SIZE(uart_config)
155#define PWM_0_EN 1
156#define PWM_1_EN 1
157
158#if PWM_0_EN
159/* PWM0 channels */
160static const pwm_conf_chan_t pwm_chan0_config[] = {
161 /* GPIO pin, MUX value, TCC channel */
162 { GPIO_PIN(PA, 4), GPIO_MUX_E, 0 },
163 { GPIO_PIN(PA, 5), GPIO_MUX_E, 1 },
164 { GPIO_PIN(PA, 19), GPIO_MUX_F, 3 },
165 { GPIO_PIN(PA, 22), GPIO_MUX_F, 4 },
166 { GPIO_PIN(PA, 23), GPIO_MUX_F, 5 },
167};
168#endif
169#if PWM_1_EN
170/* PWM1 channels */
171static const pwm_conf_chan_t pwm_chan1_config[] = {
172 /* GPIO pin, MUX value, TCC channel */
173 { GPIO_PIN(PA, 6), GPIO_MUX_E, 0 },
174 { GPIO_PIN(PA, 7), GPIO_MUX_E, 1 },
175};
176#endif
177
178/* PWM device configuration */
179static const pwm_conf_t pwm_config[] = {
180#if PWM_0_EN
181 {TCC_CONFIG(TCC0), pwm_chan0_config, ARRAY_SIZE(pwm_chan0_config), SAM0_GCLK_MAIN},
182#endif
183#if PWM_1_EN
184 {TCC_CONFIG(TCC1), pwm_chan1_config, ARRAY_SIZE(pwm_chan1_config), SAM0_GCLK_MAIN},
185#endif
186};
187
188/* number of devices that are actually defined */
189#define PWM_NUMOF ARRAY_SIZE(pwm_config)
196static const spi_conf_t spi_config[] = {
197 { /* Flash */
198 .dev = &SERCOM1->SPI,
199 .miso_pin = GPIO_PIN(PA, 18),
200 .mosi_pin = GPIO_PIN(PA, 16),
201 .clk_pin = GPIO_PIN(PA, 17),
202 .miso_mux = GPIO_MUX_C,
203 .mosi_mux = GPIO_MUX_C,
204 .clk_mux = GPIO_MUX_C,
205 .miso_pad = SPI_PAD_MISO_2,
206 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
207 .gclk_src = SAM0_GCLK_MAIN,
208#ifdef MODULE_PERIPH_DMA
209 .tx_trigger = SERCOM1_DMAC_ID_TX,
210 .rx_trigger = SERCOM1_DMAC_ID_RX,
211#endif
212 },
213 { /* D0 … D2 (user pins) */
214 .dev = &SERCOM0->SPI,
215 .miso_pin = GPIO_PIN(PA, 6), /* D2 */
216 .mosi_pin = GPIO_PIN(PA, 4), /* D0 */
217 .clk_pin = GPIO_PIN(PA, 5), /* D1 */
218 .miso_mux = GPIO_MUX_D,
219 .mosi_mux = GPIO_MUX_D,
220 .clk_mux = GPIO_MUX_D,
221 .miso_pad = SPI_PAD_MISO_2,
222 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
223 .gclk_src = SAM0_GCLK_MAIN,
224#ifdef MODULE_PERIPH_DMA
225 .tx_trigger = SERCOM0_DMAC_ID_TX,
226 .rx_trigger = SERCOM0_DMAC_ID_RX,
227#endif
228 },
229};
230
231#define SPI_NUMOF ARRAY_SIZE(spi_config)
238static const i2c_conf_t i2c_config[] = {
239 {
240 .dev = &(SERCOM2->I2CM),
241 .speed = I2C_SPEED_NORMAL,
242 .scl_pin = GPIO_PIN(PA, 9), /* D5 */
243 .sda_pin = GPIO_PIN(PA, 8), /* D4 */
244 .mux = GPIO_MUX_D,
245 .gclk_src = SAM0_GCLK_MAIN,
246 .flags = I2C_FLAG_NONE
247 }
248};
249#define I2C_NUMOF ARRAY_SIZE(i2c_config)
256#ifndef RTT_FREQUENCY
257#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
258#endif
265#define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
266
267#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
268#define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
269#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
270
271static const adc_conf_chan_t adc_channels[] = {
272 /* port, pin, muxpos */
274 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA05 },
275 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA06 },
276 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA07 },
277 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA08 },
278 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA09 },
279};
280
281#define ADC_NUMOF ARRAY_SIZE(adc_channels)
288static const sam0_common_usb_config_t sam_usbdev_config[] = {
289 {
290 .dm = GPIO_PIN(PA, 24),
291 .dp = GPIO_PIN(PA, 25),
292 .d_mux = GPIO_MUX_G,
293 .device = &USB->DEVICE,
294 .gclk_src = SAM0_GCLK_MAIN,
295 }
296};
299#ifdef __cplusplus
300}
301#endif
302
303#endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:83
@ UART_PAD_RX_1
select pad 1
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_2
use pad 2 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_E
select peripheral function E
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_G
select peripheral function G
@ GPIO_MUX_C
select peripheral function C
@ GPIO_MUX_F
select peripheral function F
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define ADC_INPUTCTRL_MUXPOS_PA05
Alias for PIN5.
Definition periph_cpu.h:124
@ SAM0_GCLK_1MHZ
1 MHz clock for xTimer
Definition periph_cpu.h:76
#define ADC_INPUTCTRL_MUXPOS_PA08
Alias for PIN16.
Definition periph_cpu.h:135
#define ADC_INPUTCTRL_MUXPOS_PA09
Alias for PIN17.
Definition periph_cpu.h:136
#define ADC_INPUTCTRL_MUXPOS_PA07
Alias for PIN7.
Definition periph_cpu.h:126
#define ADC_INPUTCTRL_MUXPOS_PA04
Alias for PIN4.
Definition periph_cpu.h:123
#define ADC_INPUTCTRL_MUXPOS_PA06
Alias for PIN6.
Definition periph_cpu.h:125
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:74
ADC Channel Configuration.
uint32_t inputctrl
ADC channel pin multiplexer value
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
PWM channel configuration data structure.
PWM device configuration.
USB peripheral parameters.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Tc * dev
pointer to the used Timer device
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219