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periph_conf.h
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1/*
2 * Copyright (C) 2024 ML!PA Consulting GmbH
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef PERIPH_CONF_H
21#define PERIPH_CONF_H
22
23#include "periph_cpu.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
33#ifndef CLOCK_CORECLOCK
34#define CLOCK_CORECLOCK MHZ(120)
35#endif
42#define EXTERNAL_OSC32_SOURCE 1
43#define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 0
50#define USE_VREG_BUCK (1)
51
56static const tc32_conf_t timer_config[] = {
57 { /* Timer 0 - System Clock */
58 .dev = TC0,
59 .irq = TC0_IRQn,
60 .mclk = &MCLK->APBAMASK.reg,
61 .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
62 .gclk_id = TC0_GCLK_ID,
63 .gclk_src = SAM0_GCLK_TIMER,
64 .flags = TC_CTRLA_MODE_COUNT32,
65 },
66 { /* Timer 1 */
67 .dev = TC2,
68 .irq = TC2_IRQn,
69 .mclk = &MCLK->APBBMASK.reg,
70 .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
71 .gclk_id = TC2_GCLK_ID,
72 .gclk_src = SAM0_GCLK_TIMER,
73 .flags = TC_CTRLA_MODE_COUNT32,
74 }
75};
76
77/* Timer 0 configuration */
78#define TIMER_0_CHANNELS 2
79#define TIMER_0_ISR isr_tc0
80
81/* Timer 1 configuration */
82#define TIMER_1_CHANNELS 2
83#define TIMER_1_ISR isr_tc2
84
85#define TIMER_NUMOF ARRAY_SIZE(timer_config)
93static const can_conf_t candev_conf[] = {
94 {
95 .can = CAN0,
96 .rx_pin = GPIO_PIN(PA, 22),
97 .tx_pin = GPIO_PIN(PB, 23),
98 .gclk_src = SAM0_GCLK_PERIPH,
99 },
100 {
101 .can = CAN1,
102 .rx_pin = GPIO_PIN(PB, 15),
103 .tx_pin = GPIO_PIN(PB, 14),
104 .gclk_src = SAM0_GCLK_PERIPH,
105 }
106};
107
109#define ISR_CAN0 isr_can0
110
112#define ISR_CAN1 isr_can1
113
115#define CAN_NUMOF ARRAY_SIZE(candev_conf)
122static const uart_conf_t uart_config[] = {
123 { /* Virtual COM Port */
124 .dev = &SERCOM5->USART,
125 .rx_pin = GPIO_PIN(PB, 16),
126 .tx_pin = GPIO_PIN(PB, 17),
127 .mux = GPIO_MUX_C,
128 .rx_pad = UART_PAD_RX_1,
129 .tx_pad = UART_PAD_TX_0,
130 .flags = UART_FLAG_NONE,
131 .gclk_src = SAM0_GCLK_PERIPH,
132 },
133 { /* shared with CAN1 */
134 .dev = &SERCOM4->USART,
135 .rx_pin = GPIO_PIN(PB, 13),
136 .tx_pin = GPIO_PIN(PB, 12),
137#ifdef MODULE_PERIPH_UART_HW_FC
138 .rts_pin = GPIO_PIN(PB, 14),
139 .cts_pin = GPIO_PIN(PB, 15),
140#endif
141 .mux = GPIO_MUX_C,
142 .rx_pad = UART_PAD_RX_1,
143#ifdef MODULE_PERIPH_UART_HW_FC
145#else
146 .tx_pad = UART_PAD_TX_0,
147#endif
148 .flags = UART_FLAG_NONE,
149 .gclk_src = SAM0_GCLK_PERIPH,
150 },
151 {
152 .dev = &SERCOM0->USART,
153 .rx_pin = GPIO_PIN(PA, 9),
154 .tx_pin = GPIO_PIN(PA, 8),
155#ifdef MODULE_PERIPH_UART_HW_FC
156 .rts_pin = GPIO_PIN(PA, 10),
157 .cts_pin = GPIO_PIN(PA, 10),
158#endif
159 .mux = GPIO_MUX_C,
160 .rx_pad = UART_PAD_RX_1,
161#ifdef MODULE_PERIPH_UART_HW_FC
163#else
164 .tx_pad = UART_PAD_TX_0,
165#endif
166 .flags = UART_FLAG_NONE,
167 .gclk_src = SAM0_GCLK_PERIPH,
168 },
169 { /* shared with CAN0 */
170 .dev = &SERCOM3->USART,
171 .rx_pin = GPIO_PIN(PA, 23),
172 .tx_pin = GPIO_PIN(PA, 22),
173 .mux = GPIO_MUX_C,
174 .rx_pad = UART_PAD_RX_1,
175 .tx_pad = UART_PAD_TX_0,
176 .flags = UART_FLAG_NONE,
177 .gclk_src = SAM0_GCLK_PERIPH,
178 }
179};
180
181/* interrupt function name mapping */
182#define UART_0_ISR isr_sercom5_2
183#define UART_0_ISR_TX isr_sercom5_0
184
185#define UART_1_ISR isr_sercom4_2
186#define UART_1_ISR_TX isr_sercom4_0
187
188#define UART_2_ISR isr_sercom0_2
189#define UART_2_ISR_TX isr_sercom0_0
190
191#define UART_3_ISR isr_sercom3_2
192#define UART_3_ISR_TX isr_sercom3_0
193
194#define UART_NUMOF ARRAY_SIZE(uart_config)
202/* PWM0 channels */
203static const pwm_conf_chan_t pwm_chan0_config[] = {
204 /* GPIO pin, MUX value, TCC channel */
205 {
206 .pin = GPIO_PIN(PA, 14), /* LED0 */
207 .mux = GPIO_MUX_F,
208 .chan = 0,
209 },
210};
211
212/* PWM device configuration */
213static const pwm_conf_t pwm_config[] = {
214 {
215 .tim = TCC_CONFIG(TCC2),
216 .chan = pwm_chan0_config,
217 .chan_numof = ARRAY_SIZE(pwm_chan0_config),
218 .gclk_src = SAM0_GCLK_48MHZ,
219 },
220};
221
222/* number of devices that are actually defined */
223#define PWM_NUMOF ARRAY_SIZE(pwm_config)
230static const spi_conf_t spi_config[] = {
231 {
232 .dev = &SERCOM1->SPI,
233 .miso_pin = GPIO_PIN(PA, 19),
234 .mosi_pin = GPIO_PIN(PA, 16),
235 .clk_pin = GPIO_PIN(PA, 27),
236 .miso_mux = GPIO_MUX_C,
237 .mosi_mux = GPIO_MUX_C,
238 .clk_mux = GPIO_MUX_C,
239 .miso_pad = SPI_PAD_MISO_3,
240 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
241 .gclk_src = SAM0_GCLK_PERIPH,
242#ifdef MODULE_PERIPH_DMA
243 .tx_trigger = SERCOM1_DMAC_ID_TX,
244 .rx_trigger = SERCOM1_DMAC_ID_RX,
245#endif
246
247 },
248};
249
250#define SPI_NUMOF ARRAY_SIZE(spi_config)
257static const i2c_conf_t i2c_config[] = {
258 {
259 .dev = &SERCOM2->I2CM,
260 .speed = I2C_SPEED_NORMAL,
261 .scl_pin = GPIO_PIN(PA, 13),
262 .sda_pin = GPIO_PIN(PA, 12),
263 .mux = GPIO_MUX_C,
264 .gclk_src = SAM0_GCLK_PERIPH,
265 .flags = I2C_FLAG_NONE
266 },
267};
268
269#define I2C_NUMOF ARRAY_SIZE(i2c_config)
276#ifndef RTT_FREQUENCY
277#define RTT_FREQUENCY (32768U)
278#endif
287static const sam0_common_usb_config_t sam_usbdev_config[] = {
288 {
289 .dm = GPIO_PIN(PA, 24),
290 .dp = GPIO_PIN(PA, 25),
291 .d_mux = GPIO_MUX_H,
292 .device = &USB->DEVICE,
293 .gclk_src = SAM0_GCLK_PERIPH,
294 }
295};
303/* ADC Default values */
304#define ADC_GCLK_SRC SAM0_GCLK_PERIPH
305#define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
306
307#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
308#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
309
310static const adc_conf_chan_t adc_channels[] = {
311 /* inputctrl, dev */
312 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA07, .dev = ADC0 },
313 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 },
314 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB09, .dev = ADC0 },
315 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA11, .dev = ADC0 },
316 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA10, .dev = ADC0 },
317 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB08, .dev = ADC0 },
318 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB03, .dev = ADC0 },
319 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA02, .dev = ADC0 },
320 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB04, .dev = ADC1 },
321 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB05, .dev = ADC1 },
322 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB06, .dev = ADC1 },
323 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB07, .dev = ADC1 },
324 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB01, .dev = ADC0 },
325 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB00, .dev = ADC0 },
326 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA03, .dev = ADC0 },
327};
328
329#define ADC_NUMOF ARRAY_SIZE(adc_channels)
336 /* Must not exceed 12 MHz */
337#define DAC_CLOCK SAM0_GCLK_TIMER
338 /* Use external reference voltage on PA03 */
339 /* (You have to manually connect PA03 with Vcc) */
340 /* Internal reference only gives 1V */
341#define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
344#ifdef __cplusplus
345}
346#endif
347
348#endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:83
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_3
use pad 3 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0_RTS_2_CTS_3
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
@ UART_PAD_TX_0
select pad 0
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_C
select peripheral function C
@ GPIO_MUX_F
select peripheral function F
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition periph_cpu.h:130
#define ADC0_INPUTCTRL_MUXPOS_PA07
Alias for AIN7.
Definition periph_cpu.h:133
#define ADC0_INPUTCTRL_MUXPOS_PA10
Alias for AIN10.
Definition periph_cpu.h:136
#define ADC1_INPUTCTRL_MUXPOS_PB05
Alias for AIN7.
Definition periph_cpu.h:150
#define ADC1_INPUTCTRL_MUXPOS_PB04
Alias for AIN6.
Definition periph_cpu.h:149
#define ADC0_INPUTCTRL_MUXPOS_PB01
Alias for AIN13.
Definition periph_cpu.h:139
#define ADC0_INPUTCTRL_MUXPOS_PB03
Alias for AIN15.
Definition periph_cpu.h:141
#define ADC0_INPUTCTRL_MUXPOS_PB08
Alias for AIN2.
Definition periph_cpu.h:128
#define ADC0_INPUTCTRL_MUXPOS_PA11
Alias for AIN11.
Definition periph_cpu.h:137
#define ADC0_INPUTCTRL_MUXPOS_PB00
Alias for AIN12.
Definition periph_cpu.h:138
#define ADC1_INPUTCTRL_MUXPOS_PB07
Alias for AIN9.
Definition periph_cpu.h:152
#define ADC0_INPUTCTRL_MUXPOS_PA03
Alias for AIN1.
Definition periph_cpu.h:127
#define ADC0_INPUTCTRL_MUXPOS_PB09
Alias for AIN3.
Definition periph_cpu.h:129
#define SAM0_GCLK_TIMER
4-8 MHz clock for xTimer
Definition periph_cpu.h:79
#define ADC0_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition periph_cpu.h:126
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition periph_cpu.h:82
#define ADC1_INPUTCTRL_MUXPOS_PB06
Alias for AIN8.
Definition periph_cpu.h:151
ADC Channel Configuration.
uint32_t inputctrl
ADC channel pin multiplexer value
ESP CAN device configuration.
Definition can_esp.h:88
Linux candev configuration.
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
PWM channel configuration data structure.
gpio_t pin
GPIO pin.
PWM device configuration.
tc_tcc_cfg_t tim
timer configuration
USB peripheral parameters.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Tc * dev
pointer to the used Timer device
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219