Loading...
Searching...
No Matches
periph_conf.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2020 ML!PA Consulting GmbH
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
22#ifndef PERIPH_CONF_H
23#define PERIPH_CONF_H
24
25#include <stdint.h>
26
27#include "cpu.h"
28#include "periph_cpu.h"
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
66#define CLOCK_USE_PLL (0)
67#define CLOCK_USE_XOSC32_DFLL (1)
68/*
69 * 0: use XOSC32K (always 32.768kHz) to clock GCLK2
70 * 1: use OSCULP32K factory calibrated (~32.768kHz) to clock GCLK2
71 *
72 * OSCULP32K is factory calibrated to be around 32.768kHz but this values can
73 * be of by a couple off % points, so prefer XOSC32K as default configuration.
74 */
75#define GEN2_ULP32K (0)
76
77#if CLOCK_USE_PLL
78/* edit these values to adjust the PLL output frequency */
79#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
80#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
81/* generate the actual used core clock frequency */
82#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
83#elif CLOCK_USE_XOSC32_DFLL
84/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
85#define CLOCK_CORECLOCK (48000000U)
86#define CLOCK_XOSC32K (32768UL)
87#define CLOCK_8MHZ (1)
88#else
89/* edit this value to your needs */
90#define CLOCK_DIV (1U)
91/* generate the actual core clock frequency */
92#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
93#endif
100static const tc32_conf_t timer_config[] = {
101 { /* Timer 0 - System Clock */
102 .dev = TC0,
103 .irq = TC0_IRQn,
104 .pm_mask = PM_APBCMASK_TC0 | PM_APBCMASK_TC1,
105 .gclk_ctrl = GCLK_CLKCTRL_ID_TC0_TC1,
106#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
107 .gclk_src = SAM0_GCLK_1MHZ,
108#else
109 .gclk_src = SAM0_GCLK_MAIN,
110#endif
111 .flags = TC_CTRLA_MODE_COUNT32,
112 },
113 { /* Timer 1 */
114 .dev = TC4,
115 .irq = TC4_IRQn,
116 .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
117 .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
118#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
119 .gclk_src = SAM0_GCLK_1MHZ,
120#else
121 .gclk_src = SAM0_GCLK_MAIN,
122#endif
123 .flags = TC_CTRLA_MODE_COUNT32,
124 }
125};
126
127/* interrupt function name mapping */
128#define TIMER_0_ISR isr_tc0
129#define TIMER_1_ISR isr_tc4
130
131#define TIMER_NUMOF ARRAY_SIZE(timer_config)
138static const uart_conf_t uart_config[] = {
139 { /* Virtual COM Port */
140 .dev = &SERCOM3->USART,
141 .rx_pin = GPIO_PIN(PA,25),
142 .tx_pin = GPIO_PIN(PA,24),
143#ifdef MODULE_PERIPH_UART_HW_FC
144 .rts_pin = GPIO_UNDEF,
145 .cts_pin = GPIO_UNDEF,
146#endif
147 .mux = GPIO_MUX_C,
148 .rx_pad = UART_PAD_RX_3,
149 .tx_pad = UART_PAD_TX_2,
150 .flags = UART_FLAG_NONE,
151 .gclk_src = SAM0_GCLK_MAIN,
152 },
153 { /* EXT1 */
154 .dev = &SERCOM4->USART,
155 .rx_pin = GPIO_PIN(PB,9),
156 .tx_pin = GPIO_PIN(PB,8),
157#ifdef MODULE_PERIPH_UART_HW_FC
158 .rts_pin = GPIO_UNDEF,
159 .cts_pin = GPIO_UNDEF,
160#endif
161 .mux = GPIO_MUX_D,
162 .rx_pad = UART_PAD_RX_1,
163 .tx_pad = UART_PAD_TX_0,
164 .flags = UART_FLAG_NONE,
165 .gclk_src = SAM0_GCLK_MAIN,
166 },
167 { /* EXT2 */
168 .dev = &SERCOM0->USART,
169 .rx_pin = GPIO_PIN(PA,9),
170 .tx_pin = GPIO_PIN(PA,8),
171#ifdef MODULE_PERIPH_UART_HW_FC
172 .rts_pin = GPIO_UNDEF,
173 .cts_pin = GPIO_UNDEF,
174#endif
175 .mux = GPIO_MUX_C,
176 .rx_pad = UART_PAD_RX_1,
177 .tx_pad = UART_PAD_TX_0,
178 .flags = UART_FLAG_NONE,
179 .gclk_src = SAM0_GCLK_MAIN,
180 },
181};
182
183/* interrupt function name mapping */
184#define UART_0_ISR isr_sercom3
185#define UART_1_ISR isr_sercom4
186#define UART_2_ISR isr_sercom0
187
188#define UART_NUMOF ARRAY_SIZE(uart_config)
195static const spi_conf_t spi_config[] = {
196 { /* EXT1 */
197 .dev = &SERCOM0->SPI,
198 .miso_pin = GPIO_PIN(PA, 4),
199 .mosi_pin = GPIO_PIN(PA, 6),
200 .clk_pin = GPIO_PIN(PA, 7),
201 .miso_mux = GPIO_MUX_D,
202 .mosi_mux = GPIO_MUX_D,
203 .clk_mux = GPIO_MUX_D,
204 .miso_pad = SPI_PAD_MISO_0,
205 .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
206 .gclk_src = SAM0_GCLK_MAIN,
207 },
208 { /* EXT2 */
209 .dev = &SERCOM1->SPI,
210 .miso_pin = GPIO_PIN(PA, 16),
211 .mosi_pin = GPIO_PIN(PA, 18),
212 .clk_pin = GPIO_PIN(PA, 19),
213 .miso_mux = GPIO_MUX_C,
214 .mosi_mux = GPIO_MUX_C,
215 .clk_mux = GPIO_MUX_C,
216 .miso_pad = SPI_PAD_MISO_0,
217 .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
218 .gclk_src = SAM0_GCLK_MAIN,
219 },
220 { /* EXT3 */
221 .dev = &SERCOM5->SPI,
222 .miso_pin = GPIO_PIN(PB, 16),
223 .mosi_pin = GPIO_PIN(PB, 22),
224 .clk_pin = GPIO_PIN(PB, 23),
225 .miso_mux = GPIO_MUX_C,
226 .mosi_mux = GPIO_MUX_D,
227 .clk_mux = GPIO_MUX_D,
228 .miso_pad = SPI_PAD_MISO_0,
229 .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
230 .gclk_src = SAM0_GCLK_MAIN,
231 },
232};
233
234#define SPI_NUMOF ARRAY_SIZE(spi_config)
241static const i2c_conf_t i2c_config[] = {
242 {
243 .dev = &(SERCOM2->I2CM),
244 .speed = I2C_SPEED_NORMAL,
245 .scl_pin = GPIO_PIN(PA, 9),
246 .sda_pin = GPIO_PIN(PA, 8),
247 .mux = GPIO_MUX_D,
248 .gclk_src = SAM0_GCLK_MAIN,
249 .flags = I2C_FLAG_NONE
250 }
251};
252#define I2C_NUMOF ARRAY_SIZE(i2c_config)
259#ifndef RTT_FREQUENCY
260#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
261#endif
268#define PWM_0_EN 1
269
270#if PWM_0_EN
271/* PWM0 channels */
272static const pwm_conf_chan_t pwm_chan0_config[] = {
273 /* GPIO pin, MUX value, TCC channel */
274 { GPIO_PIN(PA, 14), GPIO_MUX_E, 0 },
275};
276#endif
277
278/* PWM device configuration */
279static const pwm_conf_t pwm_config[] = {
280#if PWM_0_EN
281 { .tim = TC_CONFIG(TC3),
282 .chan = pwm_chan0_config,
283 .chan_numof = ARRAY_SIZE(pwm_chan0_config),
284 .gclk_src = SAM0_GCLK_1MHZ,
285 },
286#endif
287};
288
289/* number of devices that are actually defined */
290#define PWM_NUMOF ARRAY_SIZE(pwm_config)
298/* ADC Default values */
299#define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV128
300
301#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
302#define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
303#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
304
305static const adc_conf_chan_t adc_channels[] = {
306 /* port, pin, muxpos */
307 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB00 }, /* EXT1, pin 3 */
308 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB01 }, /* EXT1, pin 4 */
309 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA10 }, /* EXT2, pin 3 */
310 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA11 }, /* EXT2, pin 4 */
311 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA02 }, /* EXT3, pin 3 */
312 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA03 } /* EXT3, pin 4.*/
313};
314
315#define ADC_NUMOF ARRAY_SIZE(adc_channels)
322#define DAC_CLOCK SAM0_GCLK_1MHZ
323 /* use Vcc as reference voltage */
324#define DAC_VREF DAC_CTRLB_REFSEL_AVCC
327#ifdef __cplusplus
328}
329#endif
330
331#endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:83
@ UART_PAD_RX_1
select pad 1
@ UART_PAD_RX_3
select pad 3
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
#define TC_CONFIG(tim)
Static initializer for TC timer configuration.
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
@ UART_PAD_TX_2
select pad 2
@ GPIO_MUX_E
select peripheral function E
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_2_SCK_3
use pad 2 for MOSI, pad 3 for SCK
@ SAM0_GCLK_1MHZ
1 MHz clock for xTimer
Definition periph_cpu.h:76
#define ADC_INPUTCTRL_MUXPOS_PA10
Alias for PIN18.
Definition periph_cpu.h:137
#define ADC_INPUTCTRL_MUXPOS_PA11
Alias for PIN19.
Definition periph_cpu.h:138
#define ADC_INPUTCTRL_MUXPOS_PB01
Alias for PIN9.
Definition periph_cpu.h:128
#define ADC_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition periph_cpu.h:119
#define ADC_INPUTCTRL_MUXPOS_PA03
Alias for PIN1.
Definition periph_cpu.h:120
#define ADC_INPUTCTRL_MUXPOS_PB00
Alias for PIN8.
Definition periph_cpu.h:127
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:74
ADC Channel Configuration.
uint32_t inputctrl
ADC channel pin multiplexer value
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
PWM channel configuration data structure.
PWM device configuration.
tc_tcc_cfg_t tim
timer configuration
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Tc * dev
pointer to the used Timer device
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219