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periph_conf.h
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1/*
2 * Copyright (C) 2019 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* Add specific clock configuration (HSE, LSE) for this board here */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27#ifndef CONFIG_BOARD_HAS_HSE
28#define CONFIG_BOARD_HAS_HSE 1
29#endif
30
31#ifndef CONFIG_CLOCK_HSE
32#define CONFIG_CLOCK_HSE MHZ(32)
33#endif
34
35/* EXTAHB (HCLK2) max freq 32 Mhz*/
36#define CLOCK_EXTAHB_DIV RCC_EXTCFGR_C2HPRE_3
37#define CLOCK_EXTAHB (CLOCK_CORECLOCK / 2)
38
39#include "periph_cpu.h"
40#include "clk_conf.h"
41#include "cfg_i2c1_pb8_pb9.h"
42#include "cfg_rtt_default.h"
43#include "cfg_timer_tim2.h"
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
53static const uart_conf_t uart_config[] = {
54 {
55 .dev = USART1,
56 .rcc_mask = RCC_APB2ENR_USART1EN,
57 .rx_pin = GPIO_PIN(PORT_B, 7),
58 .tx_pin = GPIO_PIN(PORT_B, 6),
59 .rx_af = GPIO_AF7,
60 .tx_af = GPIO_AF7,
61 .bus = APB2,
62 .irqn = USART1_IRQn,
63 .type = STM32_USART,
64 .clk_src = 0, /* Use APB clock */
65 },
66 {
67 .dev = LPUART1,
68 .rcc_mask = RCC_APB1ENR2_LPUART1EN,
69 .rx_pin = GPIO_PIN(PORT_A, 3),
70 .tx_pin = GPIO_PIN(PORT_A, 2),
71 .rx_af = GPIO_AF8,
72 .tx_af = GPIO_AF8,
73 .bus = APB12,
74 .irqn = LPUART1_IRQn,
75 .type = STM32_LPUART,
76 .clk_src = 0, /* Use APB clock */
77 },
78};
79
80#define UART_0_ISR (isr_usart1)
81#define UART_1_ISR (isr_lpuart1)
82
83#define UART_NUMOF ARRAY_SIZE(uart_config)
90static const spi_conf_t spi_config[] = {
91 {
92 .dev = SPI1,
93 .mosi_pin = GPIO_PIN(PORT_A, 7),
94 .miso_pin = GPIO_PIN(PORT_A, 6),
95 .sclk_pin = GPIO_PIN(PORT_A, 5),
96 .cs_pin = SPI_CS_UNDEF,
97 .mosi_af = GPIO_AF5,
98 .miso_af = GPIO_AF5,
99 .sclk_af = GPIO_AF5,
100 .cs_af = GPIO_AF5,
101 .rccmask = RCC_APB2ENR_SPI1EN,
102 .apbbus = APB2,
103 }
104};
105
106#define SPI_NUMOF ARRAY_SIZE(spi_config)
124static const pwm_conf_t pwm_config[] = {
125 {
126 .dev = TIM1,
127 .rcc_mask = RCC_APB2ENR_TIM1EN,
128 .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* CN9 D6 */, .cc_chan = 0},
129 { .pin = GPIO_PIN(PORT_A, 9) /* CN5 D9 */, .cc_chan = 1},
130 { .pin = GPIO_PIN(PORT_A, 10) /* CN9 D3 */, .cc_chan = 2},
131 { .pin = GPIO_PIN(PORT_A, 11) /* CC10 14 */, .cc_chan = 3} },
132 .af = GPIO_AF1,
133 .bus = APB2
134 },
135};
136
137#define PWM_NUMOF ARRAY_SIZE(pwm_config)
138
145 {
146 .base_addr = (uintptr_t)USB,
147 .rcc_mask = RCC_APB1ENR1_USBEN | RCC_APB1ENR1_CRSEN,
148 .irqn = USB_LP_IRQn,
149 .apb = APB1,
150 .dm = GPIO_PIN(PORT_A, 11),
151 .dp = GPIO_PIN(PORT_A, 12),
152 .af = GPIO_AF10,
153 .disconn = GPIO_UNDEF,
154 },
155};
156
160#define USBDEV_ISR isr_usb_lp
161
165#define USBDEV_NUMOF ARRAY_SIZE(stm32_usbdev_fs_config)
166
195static const adc_conf_t adc_config[] = {
196 {GPIO_PIN(PORT_C, 0), 0, 1}, /*< ADC1_IN1 */
197 {GPIO_PIN(PORT_C, 1), 0, 2}, /*< ADC1_IN2 */
198 {GPIO_PIN(PORT_A, 1), 0, 6}, /*< ADC1_IN6 */
199 {GPIO_PIN(PORT_A, 0), 0, 5}, /*< ADC1_IN5 */
200 {GPIO_PIN(PORT_C, 3), 0, 4}, /*< ADC1_IN4 */
201 {GPIO_PIN(PORT_C, 2), 0, 3}, /*< ADC1_IN3 */
202 {GPIO_UNDEF, 0, 18}, /* VBAT */
203};
204
205#define VBAT_ADC ADC_LINE(6)
206#define ADC_NUMOF ARRAY_SIZE(adc_config)
209#ifdef __cplusplus
210}
211#endif
212
213#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const stm32_usbdev_fs_config_t stm32_usbdev_fs_config[]
USB device FS configuration.
static const adc_conf_t adc_config[]
ADC configuration.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:111
@ GPIO_AF10
use alternate function 10
Definition cpu_gpio.h:113
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:39
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:38
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
ADC device configuration.
Definition periph_cpu.h:379
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
stm32 USB device FS configuration
Definition cpu_usbdev.h:45
uintptr_t base_addr
USB peripheral base address.
Definition cpu_usbdev.h:46
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219