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periph_conf.h
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1/*
2 * Copyright (C) 2017 Freie Universität Berlin
3 * 2017 Inria
4 * 2017 HAW-Hamburg
5 * 2018 Fundacion Inria Chile
6 *
7 * This file is subject to the terms and conditions of the GNU Lesser
8 * General Public License v2.1. See the file LICENSE in the top level
9 * directory for more details.
10 */
11
25#ifndef PERIPH_CONF_H
26#define PERIPH_CONF_H
27
28/* Add specific clock configuration (HSE, LSE) for this board here */
29#ifndef CONFIG_BOARD_HAS_LSE
30#define CONFIG_BOARD_HAS_LSE 1
31#endif
32
33#include "periph_cpu.h"
34#include "clk_conf.h"
35#include "cfg_i2c1_pb8_pb9.h"
36#include "cfg_rtt_default.h"
37#include "cfg_timer_tim2.h"
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
47static const uart_conf_t uart_config[] = {
48 {
49 .dev = USART2,
50 .rcc_mask = RCC_APB1ENR1_USART2EN,
51 .rx_pin = GPIO_PIN(PORT_A, 3),
52 .tx_pin = GPIO_PIN(PORT_A, 2),
53 .rx_af = GPIO_AF7,
54 .tx_af = GPIO_AF7,
55 .bus = APB1,
56 .irqn = USART2_IRQn,
57 .type = STM32_USART,
58 .clk_src = 0, /* Use APB clock */
59 },
60 {
61 .dev = USART3,
62 .rcc_mask = RCC_APB1ENR1_USART3EN,
63 .rx_pin = GPIO_PIN(PORT_C, 11),
64 .tx_pin = GPIO_PIN(PORT_C, 10),
65 .rx_af = GPIO_AF7,
66 .tx_af = GPIO_AF7,
67 .bus = APB1,
68 .irqn = USART3_IRQn,
69 .type = STM32_USART,
70 .clk_src = 0, /* Use APB clock */
71 }
72};
73
74#define UART_0_ISR (isr_usart2)
75#define UART_1_ISR (isr_usart3)
76
77#define UART_NUMOF ARRAY_SIZE(uart_config)
84static const pwm_conf_t pwm_config[] = {
85 {
86 .dev = TIM3,
87 .rcc_mask = RCC_APB1ENR1_TIM3EN,
88 .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
89 { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
90 { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
91 { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
92 .af = GPIO_AF2,
93 .bus = APB1
94 },
95};
96
97#define PWM_NUMOF ARRAY_SIZE(pwm_config)
104static const spi_conf_t spi_config[] = {
105 {
106 .dev = SPI1,
107 .mosi_pin = GPIO_PIN(PORT_A, 7),
108 .miso_pin = GPIO_PIN(PORT_A, 6),
109 .sclk_pin = GPIO_PIN(PORT_A, 5),
110 .cs_pin = SPI_CS_UNDEF,
111 .mosi_af = GPIO_AF5,
112 .miso_af = GPIO_AF5,
113 .sclk_af = GPIO_AF5,
114 .cs_af = GPIO_AF5,
115 .rccmask = RCC_APB2ENR_SPI1EN,
116 .apbbus = APB2
117 },
118};
119
120#define SPI_NUMOF ARRAY_SIZE(spi_config)
152static const adc_conf_t adc_config[] = {
153 { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 5 }, /* A0 ADC1_IN5 */
154 { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 6 }, /* A1 ADC1_IN6 */
155 { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 9 }, /* A2 ADC1_IN9 */
156 { .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 15 }, /* A3 ADC1_IN15 */
157 { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 2 }, /* A4 ADC1_IN2 */
158 { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 1 }, /* A5 ADC1_IN1 */
159 { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 },
160};
161
165#define ADC_NUMOF ARRAY_SIZE(adc_config)
166
170#define VBAT_ADC ADC_LINE(6)
171
174#ifdef __cplusplus
175}
176#endif
177
178#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const adc_conf_t adc_config[]
ADC configuration.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:38
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
ADC device configuration.
Definition periph_cpu.h:379
gpio_t pin
pin connected to the channel
Definition periph_cpu.h:288
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219