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periph_conf.h
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1/*
2 * Copyright (C) 2022 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* This board provides an LSE */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27/* This board provides an HSE */
28#ifndef CONFIG_BOARD_HAS_HSE
29#define CONFIG_BOARD_HAS_HSE 1
30#endif
31
32#include "periph_cpu.h"
33#include "clk_conf.h"
34#include "cfg_i2c1_pb8_pb9.h"
35#include "cfg_timer_tim5.h"
36#include "cfg_usb_otg_fs.h"
37#include "mii.h"
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
47static const dma_conf_t dma_config[] = {
48 { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
49 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
50 { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
51};
52
53#define DMA_0_ISR isr_dma2_stream3
54#define DMA_1_ISR isr_dma2_stream2
55#define DMA_2_ISR isr_dma2_stream0
56
57#define DMA_NUMOF ARRAY_SIZE(dma_config)
64static const uart_conf_t uart_config[] = {
65 {
66 .dev = USART3,
67 .rcc_mask = RCC_APB1ENR_USART3EN,
68 .rx_pin = GPIO_PIN(PORT_D, 9),
69 .tx_pin = GPIO_PIN(PORT_D, 8),
70 .rx_af = GPIO_AF7,
71 .tx_af = GPIO_AF7,
72 .bus = APB1,
73 .irqn = USART3_IRQn,
74#ifdef MODULE_PERIPH_DMA
75 .dma = DMA_STREAM_UNDEF,
76 .dma_chan = UINT8_MAX,
77#endif
78 },
79 {
80 .dev = USART6,
81 .rcc_mask = RCC_APB2ENR_USART6EN,
82 .rx_pin = GPIO_PIN(PORT_G, 9),
83 .tx_pin = GPIO_PIN(PORT_G, 14),
84 .rx_af = GPIO_AF8,
85 .tx_af = GPIO_AF8,
86 .bus = APB2,
87 .irqn = USART6_IRQn,
88#ifdef MODULE_PERIPH_DMA
89 .dma = DMA_STREAM_UNDEF,
90 .dma_chan = UINT8_MAX,
91#endif
92 },
93 {
94 .dev = USART2,
95 .rcc_mask = RCC_APB1ENR_USART2EN,
96 .rx_pin = GPIO_PIN(PORT_D, 6),
97 .tx_pin = GPIO_PIN(PORT_D, 5),
98 .rx_af = GPIO_AF7,
99 .tx_af = GPIO_AF7,
100 .bus = APB1,
101 .irqn = USART2_IRQn,
102#ifdef MODULE_PERIPH_DMA
103 .dma = DMA_STREAM_UNDEF,
104 .dma_chan = UINT8_MAX,
105#endif
106 },
107};
108
109#define UART_0_ISR (isr_usart3)
110#define UART_1_ISR (isr_usart6)
111#define UART_2_ISR (isr_usart2)
112
113#define UART_NUMOF ARRAY_SIZE(uart_config)
120static const pwm_conf_t pwm_config[] = {
121 {
122 .dev = TIM1,
123 .rcc_mask = RCC_APB2ENR_TIM1EN,
124 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
125 { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
126 { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
127 { .pin = GPIO_UNDEF, .cc_chan = 0} },
128 .af = GPIO_AF1,
129 .bus = APB2
130 },
131 {
132 .dev = TIM4,
133 .rcc_mask = RCC_APB1ENR_TIM4EN,
134 .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
135 { .pin = GPIO_UNDEF, .cc_chan = 0},
136 { .pin = GPIO_UNDEF, .cc_chan = 0},
137 { .pin = GPIO_UNDEF, .cc_chan = 0} },
138 .af = GPIO_AF2,
139 .bus = APB1
140 },
141};
142
143#define PWM_NUMOF ARRAY_SIZE(pwm_config)
150static const spi_conf_t spi_config[] = {
151 {
152 .dev = SPI1,
153 .mosi_pin = GPIO_PIN(PORT_A, 7),
154 .miso_pin = GPIO_PIN(PORT_A, 6),
155 .sclk_pin = GPIO_PIN(PORT_A, 5),
156 .cs_pin = GPIO_UNDEF,
157 .mosi_af = GPIO_AF5,
158 .miso_af = GPIO_AF5,
159 .sclk_af = GPIO_AF5,
160 .cs_af = GPIO_AF5,
161 .rccmask = RCC_APB2ENR_SPI1EN,
162 .apbbus = APB2,
163#ifdef MODULE_PERIPH_DMA
164 .tx_dma = 0,
165 .tx_dma_chan = 3,
166 .rx_dma = 1,
167 .rx_dma_chan = 3,
168#endif
169 }
170};
171
172#define SPI_NUMOF ARRAY_SIZE(spi_config)
179static const eth_conf_t eth_config = {
180 .mode = RMII,
182 .dma = 2,
183 .dma_chan = 8,
184 .phy_addr = 0x00,
185 .pins = {
186 GPIO_PIN(PORT_G, 13),
187 GPIO_PIN(PORT_B, 13),
188 GPIO_PIN(PORT_G, 11),
189 GPIO_PIN(PORT_C, 4),
190 GPIO_PIN(PORT_C, 5),
191 GPIO_PIN(PORT_A, 7),
192 GPIO_PIN(PORT_C, 1),
193 GPIO_PIN(PORT_A, 2),
194 GPIO_PIN(PORT_A, 1),
195 }
196};
197
198#define ETH_DMA_ISR isr_dma2_stream0
224static const adc_conf_t adc_config[] = {
225 {GPIO_PIN(PORT_A, 3), .dev = 2, .chan = 3}, /* ADC123_IN3 */
226 {GPIO_PIN(PORT_C, 0), .dev = 2, .chan = 10}, /* ADC123_IN10 */
227 {GPIO_PIN(PORT_C, 3), .dev = 2, .chan = 13}, /* ADC123_IN13 */
228 {GPIO_PIN(PORT_F, 3), .dev = 2, .chan = 9}, /* ADC3_IN9 */
229 {GPIO_PIN(PORT_F, 5), .dev = 2, .chan = 15}, /* ADC3_IN15 */
230 {GPIO_PIN(PORT_F, 10), .dev = 2, .chan = 8}, /* ADC3_IN8 */
231 {GPIO_UNDEF, .dev = 0, .chan = 18}, /* VBAT */
232};
233
234#define VBAT_ADC ADC_LINE(6)
236#define ADC_NUMOF ARRAY_SIZE(adc_config)
239#ifdef __cplusplus
240}
241#endif
242
243#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_G
port G
Definition periph_cpu.h:53
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_F
port F
Definition periph_cpu.h:52
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
Definition cpu_eth.h:37
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:111
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
#define MII_BMCR_FULL_DPLX
Set for full duplex.
Definition mii.h:69
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Definition mii.h:73
Interface definition for MII/RMII h.
ADC device configuration.
Definition periph_cpu.h:379
ADC_TypeDef * dev
ADC device used.
Definition periph_cpu.h:380
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
Ethernet Peripheral configuration.
Definition cpu_eth.h:44
eth_mode_t mode
Select configuration mode.
Definition cpu_eth.h:45
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219