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periph_conf.h
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1/*
2 * Copyright (C) 2016 Inria
3 * Copyright (C) 2017 OTA keys S.A.
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CONF_H
22#define PERIPH_CONF_H
23
24/* This board provides an LSE */
25#ifndef CONFIG_BOARD_HAS_LSE
26#define CONFIG_BOARD_HAS_LSE 1
27#endif
28
29/* This board provides an HSE */
30#ifndef CONFIG_BOARD_HAS_HSE
31#define CONFIG_BOARD_HAS_HSE 1
32#endif
33
34#include "periph_cpu.h"
35#include "clk_conf.h"
36#include "cfg_i2c1_pb8_pb9.h"
37#include "cfg_timer_tim5.h"
38#include "cfg_usb_otg_fs.h"
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
48static const dma_conf_t dma_config[] = {
49 { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
50 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
51};
52
53#define DMA_0_ISR isr_dma2_stream3
54#define DMA_1_ISR isr_dma2_stream2
55
56#define DMA_NUMOF ARRAY_SIZE(dma_config)
63static const uart_conf_t uart_config[] = {
64 {
65 .dev = USART3,
66 .rcc_mask = RCC_APB1ENR_USART3EN,
67 .rx_pin = GPIO_PIN(PORT_D, 9),
68 .tx_pin = GPIO_PIN(PORT_D, 8),
69 .rx_af = GPIO_AF7,
70 .tx_af = GPIO_AF7,
71 .bus = APB1,
72 .irqn = USART3_IRQn,
73#ifdef MODULE_PERIPH_DMA
74 .dma = DMA_STREAM_UNDEF,
75 .dma_chan = UINT8_MAX,
76#endif
77 },
78 {
79 .dev = USART6,
80 .rcc_mask = RCC_APB2ENR_USART6EN,
81 .rx_pin = GPIO_PIN(PORT_G, 9),
82 .tx_pin = GPIO_PIN(PORT_G, 14),
83 .rx_af = GPIO_AF8,
84 .tx_af = GPIO_AF8,
85 .bus = APB2,
86 .irqn = USART6_IRQn,
87#ifdef MODULE_PERIPH_DMA
88 .dma = DMA_STREAM_UNDEF,
89 .dma_chan = UINT8_MAX,
90#endif
91 },
92 {
93 .dev = USART2,
94 .rcc_mask = RCC_APB2ENR_USART1EN,
95 .rx_pin = GPIO_PIN(PORT_D, 6),
96 .tx_pin = GPIO_PIN(PORT_D, 5),
97 .rx_af = GPIO_AF7,
98 .tx_af = GPIO_AF7,
99 .bus = APB2,
100 .irqn = USART2_IRQn,
101#ifdef MODULE_PERIPH_DMA
102 .dma = DMA_STREAM_UNDEF,
103 .dma_chan = UINT8_MAX,
104#endif
105 },
106};
107
108#define UART_0_ISR (isr_usart3)
109#define UART_1_ISR (isr_usart6)
110#define UART_2_ISR (isr_usart2)
111
112#define UART_NUMOF ARRAY_SIZE(uart_config)
119static const pwm_conf_t pwm_config[] = {
120 {
121 .dev = TIM1,
122 .rcc_mask = RCC_APB2ENR_TIM1EN,
123 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
124 { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
125 { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
126 { .pin = GPIO_UNDEF, .cc_chan = 0} },
127 .af = GPIO_AF1,
128 .bus = APB2
129 },
130 {
131 .dev = TIM4,
132 .rcc_mask = RCC_APB1ENR_TIM4EN,
133 .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
134 { .pin = GPIO_UNDEF, .cc_chan = 0},
135 { .pin = GPIO_UNDEF, .cc_chan = 0},
136 { .pin = GPIO_UNDEF, .cc_chan = 0} },
137 .af = GPIO_AF2,
138 .bus = APB1
139 },
140};
141
142#define PWM_NUMOF ARRAY_SIZE(pwm_config)
149static const spi_conf_t spi_config[] = {
150 {
151 .dev = SPI1,
152 .mosi_pin = GPIO_PIN(PORT_A, 7),
153 .miso_pin = GPIO_PIN(PORT_A, 6),
154 .sclk_pin = GPIO_PIN(PORT_A, 5),
155 .cs_pin = GPIO_PIN(PORT_A, 4),
156 .mosi_af = GPIO_AF5,
157 .miso_af = GPIO_AF5,
158 .sclk_af = GPIO_AF5,
159 .cs_af = GPIO_AF5,
160 .rccmask = RCC_APB2ENR_SPI1EN,
161 .apbbus = APB2,
162#ifdef MODULE_PERIPH_DMA
163 .tx_dma = 0,
164 .tx_dma_chan = 3,
165 .rx_dma = 1,
166 .rx_dma_chan = 3,
167#endif
168 }
169};
170
171#define SPI_NUMOF ARRAY_SIZE(spi_config)
184static const adc_conf_t adc_config[] = {
185 {GPIO_PIN(PORT_A, 3), 0, 3},
186 {GPIO_PIN(PORT_C, 0), 0, 10},
187 {GPIO_PIN(PORT_C, 3), 0, 13},
188 {GPIO_PIN(PORT_C, 1), 0, 11},
189 {GPIO_PIN(PORT_C, 4), 0, 14},
190 {GPIO_PIN(PORT_C, 5), 0, 15},
191 {GPIO_UNDEF, 0, 18}, /* VBAT */
192};
193
194#define VBAT_ADC ADC_LINE(6)
195#define ADC_NUMOF ARRAY_SIZE(adc_config)
198#ifdef __cplusplus
199}
200#endif
201
202#endif /* PERIPH_CONF_H */
@ PORT_G
port G
Definition periph_cpu.h:53
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:111
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
ADC device configuration.
Definition periph_cpu.h:379
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219