24#include "periph_cpu.h"
35static const clock_config_t clock_config = {
44 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |
45 SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
47 .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
49 KINETIS_CLOCK_OSC0_EN |
50 KINETIS_CLOCK_RTCOSC_EN |
51 KINETIS_CLOCK_USE_FAST_IRC |
53 .default_mode = KINETIS_MCG_MODE_FEE,
55 .erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
57 .oscsel = MCG_C7_OSCSEL(0),
58 .fcrdiv = MCG_SC_FCRDIV(0),
59 .fll_frdiv = MCG_C1_FRDIV(0b011),
60 .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464,
61 .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920,
62 .pll_prdiv = MCG_C5_PRDIV0(0b00011),
63 .pll_vdiv = MCG_C6_VDIV0(0b00110),
65#define CLOCK_CORECLOCK (60000000ul)
66#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
84#define LPTMR_NUMOF (1U)
85#define LPTMR_CONFIG { \
88 .irqn = LPTMR0_IRQn, \
90 .base_freq = 32768u, \
93#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
95#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
96#define PIT_ISR_0 isr_pit1
97#define PIT_ISR_1 isr_pit3
98#define LPTMR_ISR_0 isr_lptmr0
111 .pcr_rx = PORT_PCR_MUX(3),
112 .pcr_tx = PORT_PCR_MUX(3),
113 .irqn = UART1_RX_TX_IRQn,
114 .scgc_addr = &SIM->SCGC4,
115 .scgc_bit = SIM_SCGC4_UART1_SHIFT,
124 .pcr_rx = PORT_PCR_MUX(3),
125 .pcr_tx = PORT_PCR_MUX(3),
126 .irqn = UART0_RX_TX_IRQn,
127 .scgc_addr = &SIM->SCGC4,
128 .scgc_bit = SIM_SCGC4_UART0_SHIFT,
134#define UART_0_ISR (isr_uart1_rx_tx)
135#define UART_1_ISR (isr_uart0_rx_tx)
137#define UART_NUMOF ARRAY_SIZE(uart_config)
196#define ADC_NUMOF ARRAY_SIZE(adc_config)
203#define ADC_REF_SETTING 0
223#define PWM_NUMOF ARRAY_SIZE(pwm_config)
236static const uint32_t spi_clk_config[] = {
238 SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) |
239 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
240 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
241 SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
244 SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) |
245 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
246 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
247 SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
250 SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) |
251 SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
252 SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
253 SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
256 SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) |
257 SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
258 SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
259 SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
262 SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) |
263 SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
264 SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
265 SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
283 .simmask = SIM_SCGC6_SPI0_MASK
287#define SPI_NUMOF ARRAY_SIZE(spi_config)
302 .scl_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
303 .sda_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
306#define I2C_NUMOF ARRAY_SIZE(i2c_config)
307#define I2C_0_ISR (isr_i2c0)
308#define I2C_1_ISR (isr_i2c1)
#define CLOCK_CORECLOCK
Clock configuration.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
#define SPI_CS_UNDEF
Define value for unused CS line.
#define UART0
UART0 register bank.
#define UART1
UART1 register bank.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
#define ADC_AVG_NONE
Disable hardware averaging.
@ KINETIS_UART
Kinetis UART module type.
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
ADC device configuration.
ADC_TypeDef * dev
ADC device used.
I2C configuration structure.
I2C_Type * i2c
Pointer to hardware module registers.
gpio_t pin
GPIO pin mapped to this channel.
PWM device configuration.
pwm_chan_t chan[TIMER_CHANNEL_NUMOF]
channel mapping set to {GPIO_UNDEF, 0} if not used
SPI device configuration.
SPI_t * dev
pointer to the used SPI device
UART device configuration.
USART_t * dev
pointer to the used UART device