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periph_conf.h
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1/*
2 * Copyright (C) 2017 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22#include <stdint.h>
23
24#include "cpu.h"
25#include "periph_cpu.h"
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
62#define CLOCK_USE_PLL (1)
63
64#if CLOCK_USE_PLL
65/* edit these values to adjust the PLL output frequency */
66#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
67#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
68#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
69#else
70/* edit this value to your needs */
71#define CLOCK_DIV (1U)
72/* generate the actual core clock frequency */
73#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
74#endif
81static const tc32_conf_t timer_config[] = {
82 { /* Timer 0 - System Clock */
83 .dev = TC3,
84 .irq = TC3_IRQn,
85 .pm_mask = PM_APBCMASK_TC3,
86 .gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
87#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
88 .gclk_src = SAM0_GCLK_1MHZ,
89#else
90 .gclk_src = SAM0_GCLK_MAIN,
91#endif
92 .flags = TC_CTRLA_MODE_COUNT16,
93 },
94 { /* Timer 1 */
95 .dev = TC4,
96 .irq = TC4_IRQn,
97 .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
98 .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
99#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
100 .gclk_src = SAM0_GCLK_1MHZ,
101#else
102 .gclk_src = SAM0_GCLK_MAIN,
103#endif
104 .flags = TC_CTRLA_MODE_COUNT32,
105 }
106};
107
108#define TIMER_0_MAX_VALUE 0xffff
109
110/* interrupt function name mapping */
111#define TIMER_0_ISR isr_tc3
112#define TIMER_1_ISR isr_tc4
113
114#define TIMER_NUMOF ARRAY_SIZE(timer_config)
121static const uart_conf_t uart_config[] = {
122 {
123 .dev = &SERCOM0->USART,
124 .rx_pin = GPIO_PIN(PA, 11), /* RX pin */
125 .tx_pin = GPIO_PIN(PA, 10), /* TX pin */
126#ifdef MODULE_PERIPH_UART_HW_FC
127 .rts_pin = GPIO_UNDEF,
128 .cts_pin = GPIO_UNDEF,
129#endif
130 .mux = GPIO_MUX_C,
131 .rx_pad = UART_PAD_RX_3,
132 .tx_pad = UART_PAD_TX_2,
133 .flags = UART_FLAG_NONE,
134 .gclk_src = SAM0_GCLK_MAIN,
135 }
136};
137
138/* interrupt function name mapping */
139#define UART_0_ISR isr_sercom0
140
141#define UART_NUMOF ARRAY_SIZE(uart_config)
148#define PWM_0_EN 1
149#define PWM_1_EN 1
150
151#if PWM_0_EN
152/* PWM0 channels */
153static const pwm_conf_chan_t pwm_chan0_config[] = {
154 /* GPIO pin, MUX value, TCC channel */
155 { GPIO_PIN(PA, 7), GPIO_MUX_E, 1 }, /* ~9 */
156};
157#endif
158#if PWM_1_EN
159/* PWM1 channels */
160static const pwm_conf_chan_t pwm_chan1_config[] = {
161 /* GPIO pin, MUX value, TCC channel */
162 { GPIO_PIN(PA, 16), GPIO_MUX_E, 0 }, /* ~11 */
163};
164#endif
165
166/* PWM device configuration */
167static const pwm_conf_t pwm_config[] = {
168#if PWM_0_EN
169 {TCC_CONFIG(TCC0), pwm_chan0_config, ARRAY_SIZE(pwm_chan0_config), SAM0_GCLK_MAIN},
170#endif
171#if PWM_1_EN
172 {TCC_CONFIG(TCC2), pwm_chan1_config, ARRAY_SIZE(pwm_chan1_config), SAM0_GCLK_MAIN},
173#endif
174};
175
176/* number of devices that are actually defined */
177#define PWM_NUMOF ARRAY_SIZE(pwm_config)
185/* ADC Default values */
186#define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
187
188#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
189#define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
190#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
191
192static const adc_conf_chan_t adc_channels[] = {
193 /* port, pin, muxpos */
194 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA02 }, /* A0 */
195 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB08 }, /* A1 */
196 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB09 }, /* A2 */
197 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA04 }, /* A3 */
198 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA05 }, /* A4 */
199 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB02 }, /* A5 */
200 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA07 }, /* A7 */
201};
202
203#define ADC_NUMOF ARRAY_SIZE(adc_channels)
210static const spi_conf_t spi_config[] = {
211 {
212 .dev = &SERCOM4->SPI,
213 .miso_pin = GPIO_PIN(PA, 12),
214 .mosi_pin = GPIO_PIN(PB, 10),
215 .clk_pin = GPIO_PIN(PB, 11),
216 .miso_mux = GPIO_MUX_D,
217 .mosi_mux = GPIO_MUX_D,
218 .clk_mux = GPIO_MUX_D,
219 .miso_pad = SPI_PAD_MISO_0,
220 .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
221 .gclk_src = SAM0_GCLK_MAIN,
222#ifdef MODULE_PERIPH_DMA
223 .tx_trigger = SERCOM4_DMAC_ID_TX,
224 .rx_trigger = SERCOM4_DMAC_ID_RX,
225#endif
226 }
227};
228
229#define SPI_NUMOF ARRAY_SIZE(spi_config)
236static const i2c_conf_t i2c_config[] = {
237 {
238 .dev = &(SERCOM3->I2CM),
239 .speed = I2C_SPEED_NORMAL,
240 .scl_pin = GPIO_PIN(PA, 23),
241 .sda_pin = GPIO_PIN(PA, 22),
242 .mux = GPIO_MUX_C,
243 .gclk_src = SAM0_GCLK_MAIN,
244 .flags = I2C_FLAG_NONE
245 }
246};
247#define I2C_NUMOF ARRAY_SIZE(i2c_config)
254#ifndef RTT_FREQUENCY
255#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
256#endif
263static const sam0_common_usb_config_t sam_usbdev_config[] = {
264 {
265 .dm = GPIO_PIN(PA, 24),
266 .dp = GPIO_PIN(PA, 25),
267 .d_mux = GPIO_MUX_G,
268 .device = &USB->DEVICE,
269 .gclk_src = SAM0_GCLK_MAIN,
270 }
271};
274#ifdef __cplusplus
275}
276#endif
277
278#endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:83
@ UART_PAD_RX_3
select pad 3
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_2
select pad 2
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_E
select peripheral function E
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_G
select peripheral function G
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_2_SCK_3
use pad 2 for MOSI, pad 3 for SCK
#define ADC_INPUTCTRL_MUXPOS_PA05
Alias for PIN5.
Definition periph_cpu.h:124
#define ADC_INPUTCTRL_MUXPOS_PB08
Alias for PIN2.
Definition periph_cpu.h:121
@ SAM0_GCLK_1MHZ
1 MHz clock for xTimer
Definition periph_cpu.h:76
#define ADC_INPUTCTRL_MUXPOS_PB02
Alias for PIN10.
Definition periph_cpu.h:129
#define ADC_INPUTCTRL_MUXPOS_PB09
Alias for PIN3.
Definition periph_cpu.h:122
#define ADC_INPUTCTRL_MUXPOS_PA07
Alias for PIN7.
Definition periph_cpu.h:126
#define ADC_INPUTCTRL_MUXPOS_PA04
Alias for PIN4.
Definition periph_cpu.h:123
#define ADC_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition periph_cpu.h:119
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:74
ADC Channel Configuration.
uint32_t inputctrl
ADC channel pin multiplexer value
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
PWM channel configuration data structure.
PWM device configuration.
USB peripheral parameters.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Tc * dev
pointer to the used Timer device
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219