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periph_conf.h
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/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2016-2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "
periph_conf_common.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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static
const
uart_conf_t
uart_config[] = {
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{
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.
dev
= &SERCOM5->USART,
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.rx_pin =
GPIO_PIN
(
PB
,23),
/* ARDUINO_PIN_13, RX Pin */
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.tx_pin =
GPIO_PIN
(
PB
,22),
/* ARDUINO_PIN_14, TX Pin */
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#ifdef MODULE_PERIPH_UART_HW_FC
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.rts_pin =
GPIO_UNDEF
,
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.cts_pin =
GPIO_UNDEF
,
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#endif
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.mux =
GPIO_MUX_D
,
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.rx_pad =
UART_PAD_RX_3
,
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.tx_pad =
UART_PAD_TX_2
,
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.flags =
UART_FLAG_NONE
,
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.gclk_src =
SAM0_GCLK_MAIN
,
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}
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};
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/* interrupt function name mapping */
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#define UART_0_ISR isr_sercom5
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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static
const
spi_conf_t
spi_config[] = {
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{
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.
dev
= &SERCOM1->SPI,
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.miso_pin =
GPIO_PIN
(
PA
, 19),
/* ARDUINO_PIN_8, SERCOM1-MISO */
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.mosi_pin =
GPIO_PIN
(
PA
, 16),
/* ARDUINO_PIN_10, SERCOM1-MOSI */
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.clk_pin =
GPIO_PIN
(
PA
, 17),
/* ARDUINO_PIN_9, SERCOM1-SCK */
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.miso_mux =
GPIO_MUX_C
,
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.mosi_mux =
GPIO_MUX_C
,
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.clk_mux =
GPIO_MUX_C
,
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.miso_pad =
SPI_PAD_MISO_3
,
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.mosi_pad =
SPI_PAD_MOSI_0_SCK_1
,
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.gclk_src =
SAM0_GCLK_MAIN
,
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#ifdef MODULE_PERIPH_DMA
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.tx_trigger = SERCOM1_DMAC_ID_TX,
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.rx_trigger = SERCOM1_DMAC_ID_RX,
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#endif
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},
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{
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.dev = &SERCOM2->SPI,
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.miso_pin =
GPIO_PIN
(
PA
, 15),
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.mosi_pin =
GPIO_PIN
(
PA
, 12),
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.clk_pin =
GPIO_PIN
(
PA
, 13),
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.miso_mux =
GPIO_MUX_C
,
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.mosi_mux =
GPIO_MUX_C
,
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.clk_mux =
GPIO_MUX_C
,
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.miso_pad =
SPI_PAD_MISO_3
,
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.mosi_pad =
SPI_PAD_MOSI_0_SCK_1
,
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.gclk_src =
SAM0_GCLK_MAIN
,
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#ifdef MODULE_PERIPH_DMA
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.tx_trigger = SERCOM2_DMAC_ID_TX,
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.rx_trigger = SERCOM2_DMAC_ID_RX,
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#endif
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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#ifdef __cplusplus
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}
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#endif
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#endif
/* PERIPH_CONF_H */
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition
periph_cpu.h:46
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition
periph_cpu_common.h:54
periph_conf_common.h
Common peripheral configuration for the Particle Mesh.
UART_PAD_RX_3
@ UART_PAD_RX_3
select pad 3
Definition
periph_cpu_common.h:269
PB
@ PB
port B
Definition
periph_cpu_common.h:100
PA
@ PA
port A
Definition
periph_cpu_common.h:99
SPI_PAD_MISO_3
@ SPI_PAD_MISO_3
use pad 3 for MISO line
Definition
periph_cpu_common.h:443
UART_FLAG_NONE
@ UART_FLAG_NONE
No flags set.
Definition
periph_cpu_common.h:286
UART_PAD_TX_2
@ UART_PAD_TX_2
select pad 2
Definition
periph_cpu_common.h:277
GPIO_MUX_D
@ GPIO_MUX_D
select peripheral function D
Definition
periph_cpu_common.h:247
GPIO_MUX_C
@ GPIO_MUX_C
select peripheral function C
Definition
periph_cpu_common.h:246
SPI_PAD_MOSI_0_SCK_1
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
Definition
periph_cpu_common.h:450
SAM0_GCLK_MAIN
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition
periph_cpu.h:74
spi_conf_t
SPI device configuration.
Definition
periph_cpu.h:337
spi_conf_t::dev
SPI_t * dev
pointer to the used SPI device
Definition
periph_cpu.h:338
uart_conf_t
UART device configuration.
Definition
periph_cpu.h:218
uart_conf_t::dev
USART_t * dev
pointer to the used UART device
Definition
periph_cpu.h:219
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