Loading...
Searching...
No Matches
cpu_conf.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2016 Inria
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include <stdint.h>
21#include "cpu_conf_common.h"
22
23#if defined(CPU_LINE_STM32MP157Cxx)
24#include "vendor/stm32mp157cxx_cm4.h"
25#else
26#include "stm32_irqs.h"
27#endif
28
29/* add unused backup RAM as extra heap */
30#if !defined(NUM_HEAPS) && CPU_HAS_BACKUP_RAM
31#define NUM_HEAPS 2
32#endif
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
46#define CORTEXM_ISB_REQUIRED_AFTER_WFI 1
47
52#define CPU_DEFAULT_IRQ_PRIO (1U)
53/* STM32MP1 family has no flash */
54#if !defined(CPU_FAM_STM32MP1)
55#define CPU_FLASH_BASE FLASH_BASE
56#endif
57
58/* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */
59#if defined(CPU_MODEL_STM32MP157CAC)
60#define CPU_IRQ_NUMOF (150U)
61#endif
63
64/* Provide a CPU_IRQ_NUMOF for STM32H7 family ---
65 * The H7 family typically exposes up to 150 maskable interrupt lines
66 * (NVIC external interrupts). Defining this prevents undefined behavior
67 * where code expects CPU_IRQ_NUMOF to be present.
68 * NOTE: we only add this define; existing logic is left untouched.
69 */
70#if defined(CPU_FAM_STM32H7) && !defined(CPU_IRQ_NUMOF)
71# define CPU_IRQ_NUMOF (150U)
72#endif
73
78#if defined(CPU_FAM_STM32U5)
79#define FLASHPAGE_SIZE (8192U)
80#elif defined(CPU_FAM_STM32WB)
81#define FLASHPAGE_SIZE (4096U)
82#elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
83 || defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
84 || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
85 || defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
86 || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) \
87 || defined(CPU_FAM_STM32C0)
88#define FLASHPAGE_SIZE (2048U)
89#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
90 || defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
91 || defined(CPU_LINE_STM32F030x4) || defined(CPU_LINE_STM32F103xB) \
92 || defined(CPU_LINE_STM32F031x6)
93#define FLASHPAGE_SIZE (1024U)
94#elif defined(CPU_FAM_STM32L1)
95#define FLASHPAGE_SIZE (256U)
96#elif defined(CPU_FAM_STM32L0)
97#define FLASHPAGE_SIZE (128U)
98#endif
99
100#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
101#define FLASHPAGE_ERASE_STATE (0x00U)
102#endif
103
104#ifdef FLASHPAGE_SIZE
105#define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
106#endif
107
108#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
109 defined(CPU_FAM_STM32F7)
110#define PERIPH_FLASHPAGE_CUSTOM_PAGESIZES
111#define PERIPH_FLASHPAGE_NEEDS_FLASHPAGE_ADDR
112
124#if (defined(FLASH_OPTCR_DB1M) && (STM32_FLASHSIZE >= (1024 * 1024)))
125#define FLASHPAGE_DUAL_BANK 1
126#else
127#define FLASHPAGE_DUAL_BANK 0
128#endif
129
130/* stm32f7 uses single bank with 32KB to 256KB sectors on a number of devices */
131#if defined(CPU_FAM_STM32F7)
132#if defined(CPU_LINE_STM32F745xx) || \
133 defined(CPU_LINE_STM32F746xx) || \
134 defined(CPU_LINE_STM32F750xx) || \
135 defined(CPU_LINE_STM32F756xx) || \
136 defined(CPU_LINE_STM32F765xx) || \
137 defined(CPU_LINE_STM32F767xx) || \
138 defined(CPU_LINE_STM32F769xx) || \
139 defined(CPU_LINE_STM32F777xx) || \
140 defined(CPU_LINE_STM32F779xx)
141#define FLASHPAGE_MIN_SECTOR_SIZE (32 * 1024)
142#elif defined(CPU_LINE_STM32F722xx) || \
143 defined(CPU_LINE_STM32F723xx) || \
144 defined(CPU_LINE_STM32F730xx) || \
145 defined(CPU_LINE_STM32F732xx) || \
146 defined(CPU_LINE_STM32F733xx)
147#define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
148#else
149/* Intentionally error on an unknown line to prevent flashpage errors */
150#error Unknown STM32F7 Line, unable to determine FLASHPAGE_MIN_SECTOR_SIZE
151#endif
152
153#else /* CPU_FAM_STM32F7 */
154#define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
155#endif
156
157#if FLASHPAGE_DUAL_BANK
158/* Number of "large" sectors + 4 for the small sectors that together equal a
159 * single large sector. Times two to account for the two banks */
160#define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
161 (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 8)
162#else
163/* Number of "large" sectors + 4 for the small sectors that together equal a
164 * single large sector, eg: 1 MB = 7 * 128 KB sectors + 1 64 KB and 4 16 KB
165 * sectors */
166#define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
167 (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 4)
168#endif
169
170#endif
171
172/* The minimum block size which can be written depends on the family.
173 * However, the erase block is always FLASHPAGE_SIZE.
174 */
175#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
176 defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
177 defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
178 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
179#define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
180typedef uint64_t stm32_flashpage_block_t;
181#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
182 defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
183 defined(CPU_FAM_STM32F7)
184#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
185typedef uint32_t stm32_flashpage_block_t;
186#else
187#define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
188typedef uint16_t stm32_flashpage_block_t;
189#endif
190
191#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
192 defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
193 defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
194 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
195#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
196#else
197/* Writing should be always 4 bytes aligned */
198#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
199#endif
201
206#ifdef SRAM_BB_BASE
207#define CPU_HAS_BITBAND 1
208#endif
210
211#ifdef __cplusplus
212}
213#endif
214