33#if defined(CPU_FAM_STM32F0)
35 .rcc_mask = RCC_APB1ENR_CANEN,
42#if defined(CPU_FAM_STM32L4)
43 .rcc_mask = RCC_APB1ENR1_CAN1EN,
45 .rcc_mask = RCC_APB1ENR_CAN1EN,
46#if CANDEV_STM32_CHAN_NUMOF > 1
48 .master_rcc_mask = RCC_APB1ENR_CAN1EN,
53#if defined(CPU_FAM_STM32F1)
56#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F4)
65 .tx_irqn = CAN1_TX_IRQn,
66 .rx0_irqn = CAN1_RX0_IRQn,
67 .rx1_irqn = CAN1_RX1_IRQn,
68 .sce_irqn = CAN1_SCE_IRQn,
70 .en_deep_sleep_wake_up =
true,
78#if (CANDEV_STM32_CHAN_NUMOF >= 2) && (CAN_DLL_NUMOF >= 2)
81 .rcc_mask = RCC_APB1ENR_CAN2EN,
83 .master_rcc_mask = RCC_APB1ENR_CAN1EN,
88#ifndef CPU_FAM_STM32F1
91 .en_deep_sleep_wake_up =
true,
92 .tx_irqn = CAN2_TX_IRQn,
93 .rx0_irqn = CAN2_RX0_IRQn,
94 .rx1_irqn = CAN2_RX1_IRQn,
95 .sce_irqn = CAN2_SCE_IRQn,
104#if (CANDEV_STM32_CHAN_NUMOF >= 3) && (CAN_DLL_NUMOF >= 3)
107 .rcc_mask = RCC_APB1ENR_CAN3EN,
109 .master_rcc_mask = RCC_APB1ENR_CAN3EN,
115 .en_deep_sleep_wake_up =
true,
116 .tx_irqn = CAN3_TX_IRQn,
117 .rx0_irqn = CAN3_RX0_IRQn,
118 .rx1_irqn = CAN3_RX1_IRQn,
119 .sce_irqn = CAN3_SCE_IRQn,