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cfg_timer_default.h
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1/*
2 * Copyright (C) 2016 Kees Bakker, SODAQ
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef CFG_TIMER_DEFAULT_H
20#define CFG_TIMER_DEFAULT_H
21
22#include <stdint.h>
23
24#include "cpu.h"
25#include "periph_cpu.h"
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
35static const tc32_conf_t timer_config[] = {
36 { /* Timer 0 - System Clock */
37 .dev = TC3,
38 .irq = TC3_IRQn,
39 .pm_mask = PM_APBCMASK_TC3,
40 .gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
41#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
42 .gclk_src = SAM0_GCLK_1MHZ,
43#else
44 .gclk_src = SAM0_GCLK_MAIN,
45#endif
46 .flags = TC_CTRLA_MODE_COUNT16,
47 },
48 { /* Timer 1 */
49 .dev = TC4,
50 .irq = TC4_IRQn,
51 .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
52 .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
53#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
54 .gclk_src = SAM0_GCLK_1MHZ,
55#else
56 .gclk_src = SAM0_GCLK_MAIN,
57#endif
58 .flags = TC_CTRLA_MODE_COUNT32,
59 }
60};
61
62#define TIMER_0_MAX_VALUE 0xffff
63
64/* interrupt function name mapping */
65#define TIMER_0_ISR isr_tc3
66#define TIMER_1_ISR isr_tc4
67
68#define TIMER_NUMOF ARRAY_SIZE(timer_config)
71#ifdef __cplusplus
72}
73#endif
74
75#endif /* CFG_TIMER_DEFAULT_H */
@ SAM0_GCLK_1MHZ
1 MHz clock for xTimer
Definition periph_cpu.h:76
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:74
Timer device configuration.
Tc * dev
pointer to the used Timer device