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sdkconfig_esp32s2.h
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/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef SDKCONFIG_ESP32S2_H
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#define SDKCONFIG_ESP32S2_H
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#ifndef DOXYGEN
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* Mapping of Kconfig defines to the respective enumeration values */
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#if CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_2
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 2
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#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_5
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 5
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#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_10
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 10
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#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_20
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 20
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#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_40
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 40
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#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_80
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 80
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#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_160
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 160
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#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_240
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 240
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#endif
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#ifndef CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
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#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 80
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#endif
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#define CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES (8 * 1024)
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#define CONFIG_EFUSE_MAX_BLK_LEN 256
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
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#define CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES 2
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#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
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#define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
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#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
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#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
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#define CONFIG_ESP32S2_DEBUG_OCDAWARE 1
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#define CONFIG_ESP32S2_BROWNOUT_DET 1
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#define CONFIG_ESP32S2_BROWNOUT_DET_LVL 7
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#define CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM 0x0
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#define CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM 0
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#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
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#ifdef MODULE_ESP_IDF_USB
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#define CONFIG_USB_OTG_SUPPORTED 1
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#endif
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#ifdef MODULE_ESP_SPI_RAM
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#define CONFIG_ESP32S2_SPIRAM_SUPPORT 1
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#ifdef MODULE_ESP_SPI_OCT
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#define CONFIG_SPIRAM_MODE_OCT 1
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#else
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#define CONFIG_SPIRAM_MODE_QUAD 1
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#endif
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#define CONFIG_DEFAULT_PSRAM_CLK_IO 30
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#define CONFIG_DEFAULT_PSRAM_CS_IO 26
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#define CONFIG_SPIRAM_SUPPORT CONFIG_ESP32S2_SPIRAM_SUPPORT
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#endif
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#define CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB 1
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#define CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B 1
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#define CONFIG_ESP32S2_DATA_CACHE_8KB 1
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#define CONFIG_ESP32S2_DATA_CACHE_LINE_32B 1
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#define CONFIG_ESP_SYSTEM_MEMPROT_DEPCHECK 1
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#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 0
/* default enabled */
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#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK 0
/* default enabled */
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#define CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE 16
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#define CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE 4
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#ifdef __cplusplus
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}
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#endif
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#endif
/* DOXYGEN */
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#endif
/* SDKCONFIG_ESP32S2_H */
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