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periph_cpu.h
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1/*
2 * Copyright (C) 2018 Mesotic SAS
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef PERIPH_CPU_H
21#define PERIPH_CPU_H
22
23#include "periph_cpu_common.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
33#define PM_NUM_MODES (2)
40enum {
43};
49static const gpio_t sam0_adc_pins[1][10] = {
50 {
51 GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PA, 4), GPIO_PIN(PA, 5),
52 GPIO_PIN(PA, 6), GPIO_PIN(PA, 7), GPIO_PIN(PA, 8), GPIO_PIN(PA, 9),
53 GPIO_PIN(PA, 10), GPIO_PIN(PA, 11)
54 }
55};
56
61#define ADC_INPUTCTRL_MUXPOS_PA02 ADC_INPUTCTRL_MUXPOS_AIN0
62#define ADC_INPUTCTRL_MUXPOS_PA03 ADC_INPUTCTRL_MUXPOS_AIN1
63#define ADC_INPUTCTRL_MUXPOS_PA04 ADC_INPUTCTRL_MUXPOS_AIN2
64#define ADC_INPUTCTRL_MUXPOS_PA05 ADC_INPUTCTRL_MUXPOS_AIN3
65#define ADC_INPUTCTRL_MUXPOS_PA06 ADC_INPUTCTRL_MUXPOS_AIN4
66#define ADC_INPUTCTRL_MUXPOS_PA07 ADC_INPUTCTRL_MUXPOS_AIN5
67#define ADC_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_AIN6
68#define ADC_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_AIN7
69#define ADC_INPUTCTRL_MUXPOS_PA10 ADC_INPUTCTRL_MUXPOS_AIN8
70#define ADC_INPUTCTRL_MUXPOS_PA11 ADC_INPUTCTRL_MUXPOS_AIN9
72#define ADC_INPUTCTRL_MUXNEG_PA02 ADC_INPUTCTRL_MUXPOS_AIN0
73#define ADC_INPUTCTRL_MUXNEG_PA03 ADC_INPUTCTRL_MUXPOS_AIN1
74#define ADC_INPUTCTRL_MUXNEG_PA04 ADC_INPUTCTRL_MUXPOS_AIN2
75#define ADC_INPUTCTRL_MUXNEG_PA05 ADC_INPUTCTRL_MUXPOS_AIN3
76#define ADC_INPUTCTRL_MUXNEG_PA06 ADC_INPUTCTRL_MUXPOS_AIN4
77#define ADC_INPUTCTRL_MUXNEG_PA07 ADC_INPUTCTRL_MUXPOS_AIN5
78#define ADC_INPUTCTRL_MUXNEG_PA08 ADC_INPUTCTRL_MUXPOS_AIN6
79#define ADC_INPUTCTRL_MUXNEG_PA09 ADC_INPUTCTRL_MUXPOS_AIN7
85#define DAC_RES_BITS (10)
86
90#define DAC_NUMOF (1)
91
96#define RTT_MAX_VALUE (0xffffffff)
97#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
98#define RTT_MIN_FREQUENCY (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */
99#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
106static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS] = {
107 GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 16),
108 GPIO_PIN(PA, 17)
109};
110
116 /* config word 0 */
117 uint32_t secure_region_unlock : 3;
119 uint32_t reserved_0 : 1;
120 uint32_t bod33_level : 6;
121 uint32_t bod33_disable : 1;
122 uint32_t bod33_action : 2;
123 const uint32_t bod12_calibration : 9;
124 uint32_t wdt_run_standby : 1;
125 uint32_t wdt_enable : 1;
126 uint32_t wdt_always_on : 1;
127 uint32_t wdt_period : 4;
128 /* config word 1 */
129 uint32_t wdt_window : 4;
130 uint32_t wdt_ewoffset : 4;
131 uint32_t wdt_window_enable : 1;
132 uint32_t bod33_hysteresis : 1;
133 uint32_t reserved_1 : 1;
134 uint32_t ram_execute_never : 1;
135 uint32_t data_execute_never : 1;
136 uint32_t reserved_2 : 19;
137 /* config word 2 */
138 uint32_t secure_flash_as_size : 8;
139 uint32_t nsc_size : 6;
140 uint32_t reserved_3 : 2;
142 uint32_t reserved_4 : 4;
143 uint32_t secure_ram_size : 7;
144 uint32_t reserved_5 : 1;
145 /* config word 3 */
147 uint32_t reserved_6 : 31;
148 /* config word 4 */
149 uint32_t nonsec_a;
150 /* config word 5 */
151 uint32_t nonsec_b;
152 /* config word 6 */
153 uint32_t nonsec_c;
154 /* config word 7 */
155 uint32_t user_crc;
156};
157
158#ifdef __cplusplus
159}
160#endif
161
162#endif /* PERIPH_CPU_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ PA
port A
@ SAM0_GCLK_MAIN
48 MHz main clock
Definition periph_cpu.h:75
@ SAM0_GCLK_32KHZ
32 kHz clock
Definition periph_cpu.h:77
static const gpio_t sam0_adc_pins[1][20]
Pins that can be used for ADC input.
Definition periph_cpu.h:105
static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS]
RTC input pins that can be used for tamper detection and wake from Deep Sleep.
Definition periph_cpu.h:203
NVM User Row Mapping - Dedicated Entries Config values will be applied at power-on.
Definition periph_cpu.h:177
uint64_t bod33_level
BOD33 threshold level at power-on.
Definition periph_cpu.h:182
uint32_t secure_flash_as_size
Secure Flash (AS region) Size = AS*0x100.
Definition periph_cpu.h:138
uint64_t wdt_window
WDT Window at power-on.
Definition periph_cpu.h:189
uint32_t nonsec_b
Peripherals Non-Secure Status Fuses for Bridge B.
Definition periph_cpu.h:151
uint32_t data_execute_never
Data Flash is eXecute Never
Definition periph_cpu.h:135
uint64_t wdt_window_enable
WDT Window mode enabled on power-on
Definition periph_cpu.h:191
uint64_t bod33_hysteresis
BOD33 Hysteresis configuration
Definition periph_cpu.h:192
uint32_t reserved_6
Reserved
Definition periph_cpu.h:147
uint64_t bod33_action
BOD33 Action at power-on.
Definition periph_cpu.h:184
uint32_t reserved_4
Reserved
Definition periph_cpu.h:142
uint64_t wdt_period
WDT Period at power-on.
Definition periph_cpu.h:188
uint32_t non_secure_region_unlock
NVM Non-Secure Region UnLock Bits
Definition periph_cpu.h:118
uint32_t wdt_run_standby
WDT Runstdby at power-on
Definition periph_cpu.h:124
uint64_t reserved_2
Factory settings - do not change.
Definition periph_cpu.h:185
uint32_t secure_flash_data_size
Secure Data Flash Size = DS*0x100
Definition periph_cpu.h:141
uint64_t wdt_ewoffset
WDT Early Warning Interrupt Offset
Definition periph_cpu.h:190
uint32_t user_crc
CRC of NVM User Row bits 223:64 (words 2…6)
Definition periph_cpu.h:155
uint32_t user_row_write_enable
User Row Write Enable
Definition periph_cpu.h:146
uint64_t reserved_0
Factory settings - do not change.
Definition periph_cpu.h:179
uint32_t bod33_disable
BOD33 Disable at power-on.
Definition periph_cpu.h:236
uint64_t reserved_1
Factory settings - do not change.
Definition periph_cpu.h:181
uint32_t ram_execute_never
RAM is eXecute Never
Definition periph_cpu.h:134
uint32_t secure_ram_size
Secure SRAM Size = RS*0x80
Definition periph_cpu.h:143
uint64_t wdt_always_on
WDT Always-On at power-on.
Definition periph_cpu.h:187
const uint64_t bod12_calibration
Factory settings - do not change.
Definition periph_cpu.h:193
uint32_t nsc_size
Non-Secure Callable Flash (APPLICATION region) Size = ANSC*0x20.
Definition periph_cpu.h:139
uint64_t reserved_3
Factory settings - do not change.
Definition periph_cpu.h:194
uint32_t nonsec_a
Peripherals Non-Secure Status Fuses for Bridge A.
Definition periph_cpu.h:149
uint32_t nonsec_c
Peripherals Non-Secure Status Fuses for Bridge C.
Definition periph_cpu.h:153
uint64_t wdt_enable
WDT Enable at power-on.
Definition periph_cpu.h:186
uint32_t secure_region_unlock
NVM Secure Region UnLock Bits
Definition periph_cpu.h:117
uint32_t reserved_5
Reserved
Definition periph_cpu.h:144