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periph_cpu.h
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1/*
2 * Copyright (C) 2015 Freie Universität Berlin
3 * 2015 Hamburg University of Applied Sciences
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
22#ifndef PERIPH_CPU_H
23#define PERIPH_CPU_H
24
25#include "periph_cpu_common.h"
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
35#define PERIPH_SPI_NEEDS_INIT_CS
36#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
37#define PERIPH_SPI_NEEDS_TRANSFER_REG
38#define PERIPH_SPI_NEEDS_TRANSFER_REGS
44#define CPUID_LEN (16U)
45
50#define RTT_MAX_VALUE (0xffffffff)
51#define RTT_CLOCK_FREQUENCY (CHIP_FREQ_XTAL_32K) /* in Hz */
52#define RTT_MIN_FREQUENCY (1) /* in Hz */
53#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
63#define ADC_NUMOF (16U)
64
76#define DAC_NUMOF (2U)
77
78#ifndef DOXYGEN
83#define HAVE_SPI_MODE_T
84typedef enum {
85 SPI_MODE_0 = (SPI_CSR_NCPHA),
86 SPI_MODE_1 = (0),
87 SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA),
88 SPI_MODE_3 = (SPI_CSR_CPOL)
96#define HAVE_SPI_CLK_T
97typedef enum {
98 SPI_CLK_100KHZ = (100000),
99 SPI_CLK_400KHZ = (400000),
100 SPI_CLK_1MHZ = (1000000),
101 SPI_CLK_5MHZ = (5000000),
102 SPI_CLK_10MHZ = (10000000)
103} spi_clk_t;
105#endif /* ndef DOXYGEN */
106
107#ifndef DOXYGEN
112#define HAVE_ADC_RES_T
113typedef enum {
114 ADC_RES_6BIT = 0x1,
115 ADC_RES_8BIT = 0x2,
116 ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10,
117 ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12,
118 ADC_RES_14BIT = 0x4,
119 ADC_RES_16BIT = 0x8
120} adc_res_t;
122#endif /* ndef DOXYGEN */
123
127typedef struct {
128 gpio_t pin;
129 uint8_t hwchan;
131
135typedef struct {
136 Spi *dev;
137 uint8_t id;
139 gpio_t mosi;
140 gpio_t miso;
142} spi_conf_t;
143
144#ifdef __cplusplus
145}
146#endif
147
148#endif /* PERIPH_CPU_H */
spi_clk_t
SPI clock type.
Definition periph_cpu.h:352
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:357
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:356
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:354
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:355
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:353
adc_res_t
Possible ADC resolution settings.
Definition adc.h:93
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition adc.h:99
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition adc.h:95
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition adc.h:98
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition adc.h:94
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition adc.h:96
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition adc.h:97
uint16_t gpio_t
GPIO type identifier.
Definition periph_cpu.h:117
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
PWM channel configuration.
Definition periph_cpu.h:469
uint8_t hwchan
the HW channel used for a logical channel
Definition periph_cpu.h:129
SPI device configuration.
Definition periph_cpu.h:337
gpio_mux_t mux
pin MUX setting
Definition periph_cpu.h:141
uint8_t id
corresponding ID of that module
Definition periph_cpu.h:137
Spi * dev
SPI module to use.
Definition periph_cpu.h:136
gpio_t clk
pin mapped to the CLK line
Definition periph_cpu.h:138