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board.h
Go to the documentation of this file.
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/*
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* Copyright (C) 2017 Thomas Stilwell <stilwellt@openlabs.co>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "cpu.h"
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#include "
periph_conf.h
"
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
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/*
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* NMI shares a pin with DAC output and ADC input. Holding the pin low during
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* reset will cause a hang unless NMI is disabled. It can be enabled in
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* applications where the pin is not held low during reset.
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*/
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#define KINETIS_FOPT 0xFB
/* disable NMI (0xFF to enable) */
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#define LED0_PIN GPIO_PIN(PORT_B, 0)
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#define LED0_MASK (1 << 0)
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#define LED0_ON (GPIOB->PCOR = LED0_MASK)
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#define LED0_OFF (GPIOB->PSOR = LED0_MASK)
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#define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK)
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#if IS_ACTIVE(KINETIS_XTIMER_SOURCE_PIT)
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/* PIT xtimer configuration */
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#define XTIMER_DEV (TIMER_PIT_DEV(0))
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#define XTIMER_CHAN (0)
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/* Default xtimer settings should work on the PIT */
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#else
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/* LPTMR xtimer configuration */
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#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
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#define XTIMER_CHAN (0)
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/* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
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#define XTIMER_WIDTH (16)
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#define XTIMER_BACKOFF (16)
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#define XTIMER_ISR_BACKOFF (5)
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#define XTIMER_HZ (32768ul)
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#endif
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#ifndef PTB3_OUTPUT_OSC32K
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#define PTB3_OUTPUT_OSC32K (0)
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#endif
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#ifndef PTB3_OUTPUT_OSCERCLK
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#define PTB3_OUTPUT_OSCERCLK (0)
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
/* BOARD_H */
periph_conf.h
Native CPU peripheral configuration.
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