Loading...
Searching...
No Matches
nrf24l01p_settings.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2014 Hamburg University of Applied Sciences
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
28#define INITIAL_ADDRESS_WIDTH 5
29#define NRF24L01P_MAX_DATA_LENGTH 32
30#ifndef INITIAL_RF_CHANNEL
31#define INITIAL_RF_CHANNEL 5
32#endif
33#define INITIAL_RX_POWER_0dB 0
35
40#define DELAY_CS_TOGGLE_US 2
41#define DELAY_AFTER_FUNC_US 2
42#define DELAY_CE_HIGH_US (20)
43#define DELAY_CHANGE_PWR_MODE_US (1500)
44#define DELAY_CHANGE_TXRX_US (130)
45#define DELAY_CE_START_US (5)
46/*
47 * This is the time which is needed to physically transmit the data.
48 * Compare nrf24l01+ pruduct specification p.42. It is computed just
49 * for this setup
50 */
51#define DELAY_DATA_ON_AIR (1300)
53
58#define CMD_R_REGISTER 0x00
59#define CMD_W_REGISTER 0x20
60#define CMD_R_RX_PAYLOAD 0x61
61#define CMD_W_TX_PAYLOAD 0xa0
62#define CMD_FLUSH_TX 0xe1
63#define CMD_FLUSH_RX 0xe2
64#define CMD_REUSE_TX_PL 0xe3
65#define CMD_R_RX_PL_WID 0x60
66#define CMD_W_ACK_PAYLOAD 0xa8
67#define CMD_W_TX_PAYLOAD_NOACK 0xb0
68#define CMD_NOOP 0xff
69
70#define REGISTER_MASK 0x1F
72
77#define REG_CONFIG 0x00
78#define REG_EN_AA 0x01
79#define REG_EN_RXADDR 0x02
80#define REG_SETUP_AW 0x03
81#define REG_SETUP_RETR 0x04
82#define REG_RF_CH 0x05
83#define REG_RF_SETUP 0x06
84#define REG_STATUS 0x07
85#define REG_OBSERVE_TX 0x08
86#define REG_RPD 0x09
87#define REG_RX_ADDR_P0 0x0a
88#define REG_RX_ADDR_P1 0x0b
89#define REG_RX_ADDR_P2 0x0c
90#define REG_RX_ADDR_P3 0x0d
91#define REG_RX_ADDR_P4 0x0e
92#define REG_RX_ADDR_P5 0x0f
93#define REG_TX_ADDR 0x10
94#define REG_RX_PW_P0 0x11
95#define REG_RX_PW_P1 0x12
96#define REG_RX_PW_P2 0x13
97#define REG_RX_PW_P3 0x14
98#define REG_RX_PW_P4 0x15
99#define REG_RX_PW_P5 0x16
100#define REG_FIFO_STATUS 0x17
101#define REG_DYNPD 0x1c
102#define REG_FEATURE 0x1d
104
109#define ENAA_P0 0x01
110#define ENAA_P1 0x02
111#define ENAA_P2 0x04
112#define ENAA_P3 0x08
113#define ENAA_P4 0x10
114#define ENAA_P5 0x20
116
121#define MASK_RX_DR 0x40
122#define MASK_TX_DS 0x20
123#define MASK_MAX_RT 0x10
124#define EN_CRC 0x08
125#define CRCO 0x04
126#define PWR_UP 0x02
127#define PRIM_RX 0x01
129
134#define RX_DR 0x40
135#define TX_DS 0x20
136#define MAX_RT 0x10
137#define RX_P_NO 0x0e
138#define TX_FULL 0x01
139#define ALL_INT_MASK 0x70
141
146#define RF_SETUP_CONT_WAVE (1 << 7)
147#define RF_SETUP_RF_DR_LOW (1 << 5)
148#define RF_SETUP_PLL_LOCK (1 << 4)
149#define RF_SETUP_RF_DR_HIGH (1 << 3)
150#define RF_SETUP_RF_PWR (3 << 1)
152
156#define RF_CH_MASK 0x7f
157
162#define DYNPD_DPL_P5 (1 << 5)
163#define DYNPD_DPL_P4 (1 << 4)
164#define DYNPD_DPL_P3 (1 << 3)
165#define DYNPD_DPL_P2 (1 << 2)
166#define DYNPD_DPL_P1 (1 << 1)
167#define DYNPD_DPL_P0 (1 << 0)
169
174#define FEATURE_EN_DPL (1 << 2)
175#define FEATURE_EN_ACK_PAY (1 << 1)
176#define FEATURE_EN_DYN_ACK (1 << 0)
178
179#ifdef __cplusplus
180}
181#endif
182