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board.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2014 Eistec AB
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser General
5 * Public License v2.1. See the file LICENSE in the top level directory for more
6 * details.
7 */
8
19#ifndef BOARD_H
20#define BOARD_H
21
22#include "cpu.h"
23#include "periph_conf.h"
24#include "mulle-nvram.h"
25
26/* Use the on board RTC 32kHz clock for LPTMR clocking. */
27#undef LPTIMER_CLKSRC
29#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
30
32#define DISABLE_WDOG 1
33
37#define STDIO_UART_DEV UART_DEV(1)
38
43#if 0
44/* LPTMR xtimer configuration */
45/* WIP, Use PIT for now */
46#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
47/* LPTMR is 16 bits wide */
48#define XTIMER_WIDTH (16)
49#define XTIMER_BACKOFF (4)
50#define XTIMER_ISR_BACKOFF (4)
51#define XTIMER_HZ (32768ul)
52#else
53/* PIT xtimer configuration */
54#define XTIMER_DEV (TIMER_PIT_DEV(0))
55#define XTIMER_CHAN (0)
56#define XTIMER_BACKOFF (40)
57#define XTIMER_ISR_BACKOFF (40)
58#endif
65#define LED_PORT PTC
66#define LED0_BIT (15)
67#define LED1_BIT (14)
68#define LED2_BIT (13)
69
70#define LED0_PIN GPIO_PIN(PORT_C, LED0_BIT)
71#define LED1_PIN GPIO_PIN(PORT_C, LED1_BIT)
72#define LED2_PIN GPIO_PIN(PORT_C, LED2_BIT)
73
74#define LED0_ON (LED_PORT->PSOR = (1 << LED0_BIT))
75#define LED0_OFF (LED_PORT->PCOR = (1 << LED0_BIT))
76#define LED0_TOGGLE (LED_PORT->PTOR = (1 << LED0_BIT))
77
78#define LED1_ON (LED_PORT->PSOR = (1 << LED1_BIT))
79#define LED1_OFF (LED_PORT->PCOR = (1 << LED1_BIT))
80#define LED1_TOGGLE (LED_PORT->PTOR = (1 << LED1_BIT))
81
82#define LED2_ON (LED_PORT->PSOR = (1 << LED2_BIT))
83#define LED2_OFF (LED_PORT->PCOR = (1 << LED2_BIT))
84#define LED2_TOGGLE (LED_PORT->PTOR = (1 << LED2_BIT))
87#ifdef __cplusplus
88extern "C" {
89#endif
90
91#ifdef __cplusplus
92}
93#endif
94
104#define AT86RF2XX_PARAM_CS SPI_HWCS(1)
105#define AT86RF2XX_PARAM_INT GPIO_PIN(PORT_B, 9)
106#define AT86RF2XX_PARAM_SLEEP GPIO_PIN(PORT_E, 6)
107#define AT86RF2XX_PARAM_RESET GPIO_PIN(PORT_C, 12)
114#define LIS3DH_PARAM_INT1 GPIO_PIN(PORT_C, 18)
115#define LIS3DH_PARAM_INT2 GPIO_PIN(PORT_C, 17)
116#define LIS3DH_PARAM_CS SPI_HWCS(0)
117#define LIS3DH_PARAM_CLK (SPI_CLK_5MHZ)
124#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17)
125#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7)
126#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16)
133#define MULLE_NVRAM_SPI_DEV SPI_DEV(0)
134#define MULLE_NVRAM_SPI_CLK SPI_CLK_5MHZ
135#define MULLE_NVRAM_SPI_CS SPI_HWCS(3)
136#define MULLE_NVRAM_CAPACITY 512
137#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1
144#define MULLE_NOR_SPI_DEV SPI_DEV(0)
145#define MULLE_NOR_SPI_CLK SPI_CLK_5MHZ
146#define MULLE_NOR_SPI_CS SPI_HWCS(2)
152#define MTD_0 mtd_dev_get(0)
159#define MULLE_VBAT_ADC_LINE ADC_LINE(6)
160#define MULLE_VCHR_ADC_LINE ADC_LINE(7)
162#endif /* BOARD_H */
Native CPU peripheral configuration.
NVRAM offsets for the Eistec Mulle IoT board.