mfrc522_regs.h

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/*
 * SPDX-FileCopyrightText: 2021 Freie Universität Berlin
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include "bitarithm.h"
 
#ifdef __cplusplus
extern "C"
{
#endif

typedef enum {
    /* Command and status register definitions (page 36, table 20) */
    MFRC522_REG_COMMAND             = 0x01, 
    MFRC522_REG_COML_EN             = 0x02, 
    MFRC522_REG_DIVL_EN             = 0x03, 
    MFRC522_REG_COM_IRQ             = 0x04, 
    MFRC522_REG_DIV_IRQ             = 0x05, 
    MFRC522_REG_ERROR               = 0x06, 
    MFRC522_REG_STATUS_1            = 0x07, 
    MFRC522_REG_STATUS_2            = 0x08, 
    MFRC522_REG_FIFO_DATA           = 0x09, 
    MFRC522_REG_FIFO_LEVEL          = 0x0A, 
    MFRC522_REG_WATER_LEVEL         = 0x0B, 
    MFRC522_REG_CONTROL             = 0x0C, 
    MFRC522_REG_BIT_FRAMING         = 0x0D, 
    MFRC522_REG_COLL                = 0x0E, 
 
    /* Command register definitions (page 36, table 20) */
    MFRC522_REG_MODE                = 0x11, 
    MFRC522_REG_TX_MODE             = 0x12, 
    MFRC522_REG_RX_MODE             = 0x13, 
    MFRC522_REG_TX_CONTROL          = 0x14, 
    MFRC522_REG_TX_ASK              = 0x15, 
    MFRC522_REG_TX_SEL              = 0x16, 
    MFRC522_REG_RX_SEL              = 0x17, 
    MFRC522_REG_RX_THRESHHOLD       = 0x18, 
    MFRC522_REG_DEMOD               = 0x19, 
    MFRC522_REG_MF_TX               = 0x1C, 
    MFRC522_REG_MF_RX               = 0x1D, 
    MFRC522_REG_SERIAL_SPEED        = 0x1F, 
 
    /* Configuration register definitions (page 36-37, table 20) */
    MFRC522_REG_CRC_RESULT_MSB      = 0x21, 
    MFRC522_REG_CRC_RESULT_LSB      = 0x22, 
    MFRC522_REG_MOD_WIDTH           = 0x24, 
    MFRC522_REG_RF_CFG              = 0X26, 
    MFRC522_REG_GS_N                = 0x27, 
    MFRC522_REG_CW_GS_P             = 0x28, 
    MFRC522_REG_MOD_GS_P            = 0x29, 
    MFRC522_REG_T_MODE              = 0x2A, 
    MFRC522_REG_T_PRESCALER         = 0x2B, 
    MFRC522_REG_T_RELOAD_MSB        = 0x2C, 
    MFRC522_REG_T_RELOAD_LSB        = 0x2D, 
    MFRC522_REG_T_COUNTER_VAL_MSB   = 0x2E, 
    MFRC522_REG_T_COUNTER_VAL_LSB   = 0x2F, 
 
    /* Test register definitions (page 37, table 20) */
    MFRC522_REG_TEST_SEL_1          = 0x31, 
    MFRC522_REG_TEST_SEL_2          = 0x32, 
    MFRC522_REG_TEST_PIN_EN         = 0x33, 
    MFRC522_REG_TEST_PIN_VALUE      = 0x34, 
    MFRC522_REG_TEST_BUS            = 0x35, 
    MFRC522_REG_AUTO_TEST           = 0x36, 
    MFRC522_REG_VERSION             = 0x37, 
    MFRC522_REG_ANALOG_TEST         = 0x38, 
    MFRC522_REG_TEST_DAC_1          = 0x39, 
    MFRC522_REG_TEST_DAC2           = 0x3A, 
    MFRC522_REG_TEST_ADC            = 0x3B, 
} mfrc522_pcd_register_t;


typedef enum {
    /* Command codes (page 70, table 149) */
    MFRC522_CMD_IDLE                = 0x00, 
    MFRC522_CMD_MEM                 = 0x01, 
    MFRC522_CMD_GENERATE_RANDOM_ID  = 0x02, 
    MFRC522_CMD_CALC_CRC            = 0x03, 
    MFRC522_CMD_TRANSMIT            = 0x04, 
    MFRC522_CMD_NO_CMD_CHANGE       = 0x07, 
    MFRC522_CMD_RECEIVE             = 0x08, 
    MFRC522_CMD_TRANSCEIVE          = 0x0C, 
    MFRC522_CMD_MF_AUTHENT          = 0x0E, 
    MFRC522_CMD_SOFT_RESET          = 0x0F, 
} mfrc522_pcd_command_t;


typedef enum {
    /* Receiver gain definition (page 70, table 149) */
    MFRC522_RXGAIN_18_DB    = 0x00,                     
    MFRC522_RXGAIN_23_DB    = 0x01,                     
    MFRC522_RXGAIN_18_DB_2  = 0x02,                     
    MFRC522_RXGAIN_23_DB_2  = 0x03,                     
    MFRC522_RXGAIN_33_DB    = 0x04,                     
    MFRC522_RXGAIN_38_DB    = 0x05,                     
    MFRC522_RXGAIN_43_DB    = 0x06,                     
    MFRC522_RXGAIN_48_DB    = 0x07,                     
    MFRC522_RXGAIN_MIN      = MFRC522_RXGAIN_18_DB,     
    MFRC522_RXGAIN_AVG      = MFRC522_RXGAIN_33_DB,     
    MFRC522_RXGAIN_MAX      = MFRC522_RXGAIN_48_DB,     
} mfrc522_pcd_rx_gain_t;


typedef enum {
    /* Commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4) */
    MFRC522_PICC_CMD_ISO_14443_REQA     = 0x26,     
    MFRC522_PICC_CMD_ISO_14443_WUPA     = 0x52,     
    MFRC522_PICC_CMD_ISO_14443_SEL_CL1  = 0x93,     
    MFRC522_PICC_CMD_ISO_14443_SEL_CL2  = 0x95,     
    MFRC522_PICC_CMD_ISO_14443_SEL_CL3  = 0x97,     
    MFRC522_PICC_CMD_ISO_14443_HLTA     = 0x50,     
    MFRC522_PICC_CMD_ISO_14443_RATS     = 0xE0,     
 
    /* Commands used for MIFARE Classic EV1 (https://www.nxp.com/docs/en/data-sheet/MF1S50YYX_V1.pdf, page 13, table 9) */
    MFRC522_PICC_CMD_MF_AUTH_KEY_A      = 0x60,     
    MFRC522_PICC_CMD_MF_AUTH_KEY_B      = 0x61,     
    MFRC522_PICC_CMD_MF_PERS_UID_USAGE  = 0x40,     
    MFRC522_PICC_CMD_MF_SET_MOD_TYPE    = 0x43,     
    MFRC522_PICC_CMD_MF_READ            = 0x30,     
    MFRC522_PICC_CMD_MF_WRITE           = 0xA0,     
    MFRC522_PICC_CMD_MF_DECREMENT       = 0xC0,     
    MFRC522_PICC_CMD_MF_INCREMENT       = 0xC1,     
    MFRC522_PICC_CMD_MF_RESTORE         = 0xC2,     
    MFRC522_PICC_CMD_MF_TRANSFER        = 0xB0,     
 
    /* Commands used for MIFARE Ultralight (https://www.nxp.com/docs/en/data-sheet/MF0ICU1.pdf, Section 7.6) */
    MFRC522_PICC_CMD_MF_UL_WRITE        = 0xA2,                         
    MFRC522_PICC_CMD_MF_UL_READ         = MFRC522_PICC_CMD_MF_READ,     
    MFRC522_PICC_CMD_MF_UL_COMPAT_WRITE = MFRC522_PICC_CMD_MF_WRITE,    
} mfrc522_picc_command_t;


#define MFRC522_FIFO_BUF_SIZE   64

# define MFRC522_PICC_CASCADE_TAG   0x88

#define MFRC522_BIT_COMMAND_RCV_OFF         BIT5

#define MFRC522_BIT_COMMAND_POWER_DOWN      BIT4

#define MFRC522_BITMASK_COMMAND_POWER_DOWN  0x0F

#define MFRC522_BIT_COML_EN_IRQ_INV         BIT7

#define MFRC522_BIT_COML_EN_TX_I_EN         BIT6

#define MFRC522_BIT_COML_EN_RX_I_EN         BIT5

#define MFRC522_BIT_COML_EN_IDLE_I_EN       BIT4

#define MFRC522_BIT_COML_EN_HI_ALERT_I_EN   BIT3

#define MFRC522_BIT_COML_EN_LO_ALERT_I_EN   BIT2

#define MFRC522_BIT_COML_EN_ERR_I_EN        BIT1

#define MFRC522_BIT_COML_EN_TIMER_I_EN      BIT0

#define MFRC522_BIT_DIVL_EN_IRQ_PUSH_PULL   BIT7

#define MFRC522_BIT_DIVL_EN_MFIN_ACT_I_EN   BIT4

#define MFRC522_BIT_DIVL_EN_CRC_I_EN        BIT2

#define MFRC522_BIT_COM_IRQ_SET_1           BIT7

#define MFRC522_BIT_COM_IRQ_TX_IRQ          BIT6

#define MFRC522_BIT_COM_IRQ_RX_IRQ          BIT5

#define MFRC522_BIT_COM_IRQ_IDLE_IRQ        BIT4

#define MFRC522_BIT_COM_IRQ_HI_ALERT_IRQ    BIT3

#define MFRC522_BIT_COM_IRQ_LO_ALERT_IRQ    BIT2

#define MFRC522_BIT_COM_IRQ_ERR_IRQ         BIT1

#define MFRC522_BIT_COM_IRQ_TIMER_IRQ       BIT0

#define MFRC522_BIT_DIV_IRQ_SET_2           BIT7

#define MFRC522_BIT_DIV_IRQ_MFIN_ACT_IRQ    BIT4

#define MFRC522_BIT_DIV_IRQ_CRC_IRQ         BIT2

#define MFRC522_BIT_ERROR_WR_ERR        BIT7

#define MFRC522_BIT_ERROR_TEMP_ERR      BIT6

#define MFRC522_BIT_ERROR_BUFFER_OVFL   BIT4

#define MFRC522_BIT_ERROR_COLL_ERR      BIT3

#define MFRC522_BIT_ERROR_CRC_ERR       BIT2

#define MFRC522_BIT_ERROR_PARITY_ERR    BIT1

#define MFRC522_BIT_ERROR_PROTOCOL_ERR  BIT0

#define MFRC522_BIT_STATUS_1_CRC_OK     BIT6

#define MFRC522_BIT_STATUS_1_CRC_READY  BIT5

#define MFRC522_BIT_STATUS_1_IRQ       BIT4

#define MFRC522_BIT_STATUS_1_T_RUNNING  BIT3

#define MFRC522_BIT_STATUS_1_HI_ALERT   BIT1

#define MFRC522_BIT_STATUS_1_LO_ALERT   BIT0

#define MFRC522_BIT_STATUS_2_TEMP_SENS_CLEAR    BIT7

#define MFRC522_BIT_STATUS_2_I2C_FORCE_HS       BIT6

#define MFRC522_BIT_STATUS_2_MF_CRYPTO_1_ON     BIT3

#define MFRC522_BITMASK_STATUS_2_MODEM_STATE_2  0x07

#define MFRC522_BITMASK_FIFO_DATA   0xFF

#define MFRC522_BIT_FIFO_LEVEL_FLUSH_BUFFER BIT7

#define MFRC522_BITMASK_FIFO_LEVEL_FIFO_LEVEL  0x7F

#define MFRC522_BITMASK_WATER_LEVEL_WATER_LEVEL     0x3F

#define MFRC522_BIT_CONTROL_T_STOP_NOW          BIT7

#define MFRC522_BIT_CONTROL_T_START_NOW         BIT6

#define MFRC522_BITMASK_CONTROL_RX_LAST_BITS    0x07

#define MFRC522_BIT_BIT_FRAMING_START_SEND      BIT7

#define MFRC522_BITMASK_BIT_FRAMING_RX_ALIGN    0x70

#define MFRC522_BIT_BIT_FRAMING_TX_LAST_BITS    0x07

#define MFRC522_BIT_COLL_VALUES_AFTER_COLL      BIT7

#define MFRC522_BIT_COLL_COLL_POS_NOT_VALID     BIT5

#define MFRC522_BITMASK_COLL_COLL_POS           0x1F

#define MFRC522_BIT_MODE_MSB_FIRST          BIT7

#define MFRC522_BIT_MODE_TX_WAIT_RF         BIT5

#define MFRC522_BIT_MODE_POL_MFIN           BIT3

#define MFRC522_BITMASK_MODE_CRC_PRESET     0x03

#define MFRC522_BIT_TX_MODE_TX_CRC_EN       BIT7

#define MFRC522_BITMASK_TX_MODE_TX_SPEED    0x70

#define MFRC522_BIT_TX_MODE_INV_MOD         BIT3

#define MFRC522_BIT_RX_MODE_RX_CRC_EN       BIT7

#define MFRC522_BITMASK_RX_MODE_RX_SPEED    0x70

#define MFRC522_BIT_RX_MODE_RX_NO_ERR       BIT3

#define MFRC522_BIT_RX_MODE_RX_MULTIPLE     BIT2

#define MFRC522_BIT_TX_CONTROL_INV_TX2_RF_ON    BIT7

#define MFRC522_BIT_TX_CONTROL_INV_TX1_RF_ON    BIT6

#define MFRC522_BIT_TX_CONTROL_INV_TX2_RF_OFF   BIT5

#define MFRC522_BIT_TX_CONTROL_INV_TX1_RF_OFF   BIT4

#define MFRC522_BIT_TX_CONTROL_TX2_CW           BIT3

#define MFRC522_BIT_TX_CONTROL_TX2_RF_EN        BIT1

#define MFRC522_BIT_TX_CONTROL_TX1_RF_EN        BIT0

#define MFRC522_BIT_TX_ASK_FORCE_100_ASK    BIT6

#define MFRC522_BITMASK_TX_SEL_DRIVER_SEL   0x30

#define MFRC522_BITMASK_TX_SEL_MF_OUT_SEL   0x0F

#define MFRC522_BITMASK_RX_SEL_UART_SEL     0xC0

#define MFRC522_BITMASK_RX_SEL_RX_WAIT      0x3F

#define MFRC522_BITMASK_RX_THRESHHOLD_MIN_LEVEL     0xF0

#define MFRC522_BITMASK_RX_THRESHHOLD_COLL_LEVEL    0x07

#define MFRC522_BITMASK_DEMOD_ADD_IQ        0xC0

#define MFRC522_BIT_DEMOD_FIX_IQ            BIT5

#define MFRC522_BIT_DEMOD_T_PRESCAL_EVEN    BIT4

#define MFRC522_BITMASK_DEMOD_TAU_RCV       0x0C

#define MFRC522_BITMASK_DEMOD_TAU_SYNC      0x03

#define MFRC522_BITMASK_MF_TX_TX_WAIT   0x03

#define MFRC522_BIT_MF_RX_PARITY_DISABLE    BIT4

#define MFRC522_BITMASK_SERIAL_SPEED_BR_T0  0xE0

#define MFRC522_BITMASK_SERIAL_SPEED_BR_T1  0x1F

#define MFRC522_BITMASK_CRC_RESULT_MSB_CRC_RESULT_MSB   0xFF

#define MFRC522_BITMASK_CRC_RESULT_LSB_CRC_RESULT_LSB   0xFF

#define MFRC522_BITMASK_MOD_WIDTH   0xFF

#define MFRC522_BITMASK_RF_CFG_RX_GAIN  0x70

#define MFRC522_BITMASK_GS_N_CW_GS_N    0xF0

#define MFRC522_BITMASK_GS_N_MOD_GS_N   0x0F

#define MFRC522_BITMASK_CW_GS_P_CW_GS_P     0x3F

#define MFRC522_BITMASK_MOD_GS_P_MOD_GS_P   0x3F

#define MFRC522_BIT_T_MODE_T_AUTO                   BIT7

#define MFRC522_BITMASK_T_MODE_T_GATED              0x60

#define MFRC522_BIT_T_MODE_T_AUTO_RESTART           BIT4

#define MFRC522_BITMASK_T_MODE_T_PRESCALER_HI       0x0F

#define MFRC522_BITMASK_T_PRESCALER_T_PRESCALER_LO  0xFF

#define MFRC522_BITMASK_T_RELOAD_MSB_T_RELOAD_VAL_HI    0xFF

#define MFRC522_BITMASK_T_RELOAD_LSB_T_RELOAD_VAL_LO    0xFF

#define MFRC522_BITMASK_T_COUNTER_VAL_MSB_T_COUNTER_VAL_HI  0xFF

#define MFRC522_BITMASK_T_COUNTER_VAL_LSB_T_COUNTER_VAL_LO  0xFF
 
#ifdef __cplusplus
}
#endif