Toggle navigation
Documentation
The friendly Operating System for the Internet of Things
Loading...
Searching...
No Matches
l3gxxxx_regs.h
Go to the documentation of this file.
1
/*
2
* Copyright (C) 2018 Gunar Schorcht
3
*
4
* This file is subject to the terms and conditions of the GNU Lesser
5
* General Public License v2.1. See the file LICENSE in the top level
6
* directory for more details.
7
*/
8
17
#ifndef L3GXXXX_REGS_H
18
#define L3GXXXX_REGS_H
19
20
#ifdef __cplusplus
21
extern
"C"
22
{
23
#endif
24
29
#define L3GXXXX_REG_WHO_AM_I (0x0f)
30
#define L3GXXXX_REG_CTRL1 (0x20)
31
#define L3GXXXX_REG_CTRL2 (0x21)
32
#define L3GXXXX_REG_CTRL3 (0x22)
33
#define L3GXXXX_REG_CTRL4 (0x23)
34
#define L3GXXXX_REG_CTRL5 (0x24)
35
#define L3GXXXX_REG_REFERENCE (0x25)
36
#define L3GXXXX_REG_OUT_TEMP (0x26)
37
#define L3GXXXX_REG_STATUS (0x27)
38
#define L3GXXXX_REG_OUT_X_L (0x28)
39
#define L3GXXXX_REG_OUT_X_H (0x29)
40
#define L3GXXXX_REG_OUT_Y_L (0x2a)
41
#define L3GXXXX_REG_OUT_Y_H (0x2b)
42
#define L3GXXXX_REG_OUT_Z_L (0x2c)
43
#define L3GXXXX_REG_OUT_Z_H (0x2d)
44
#define L3GXXXX_REG_FIFO_CTRL (0x2e)
45
#define L3GXXXX_REG_FIFO_SRC (0x2f)
46
#define L3GXXXX_REG_IG_CFG (0x30)
47
#define L3GXXXX_REG_IG_SRC (0x31)
48
#define L3GXXXX_REG_IG_THS_XH (0x32)
49
#define L3GXXXX_REG_IG_THS_XL (0x33)
50
#define L3GXXXX_REG_IG_THS_YH (0x34)
51
#define L3GXXXX_REG_IG_THS_YL (0x35)
52
#define L3GXXXX_REG_IG_THS_ZH (0x36)
53
#define L3GXXXX_REG_IG_THS_ZL (0x37)
54
#define L3GXXXX_REG_IG_DURATION (0x38)
55
#define L3GXXXX_REG_LOW_ODR (0x39)
62
#define L3GXXXX_ZYXOR (0x80)
63
#define L3GXXXX_ZOR (0x40)
64
#define L3GXXXX_YOR (0x20)
65
#define L3GXXXX_XOR (0x10)
66
#define L3GXXXX_ZYXDA (0x08)
67
#define L3GXXXX_ZDA (0x04)
68
#define L3GXXXX_YDA (0x02)
69
#define L3GXXXX_XDA (0x01)
71
#define L3GXXXX_ANY_DATA_READY (0x07)
72
#define L3GXXXX_ANY_DATA_READY_S (0)
74
#define L3GXXXX_ODR (0xc0)
75
#define L3GXXXX_BW (0x30)
76
#define L3GXXXX_ODR_BW (0xf0)
77
#define L3GXXXX_POWER_MODE (0x08)
78
#define L3GXXXX_Z_ENABLED (0x04)
79
#define L3GXXXX_Y_ENABLED (0x02)
80
#define L3GXXXX_X_ENABLED (0x01)
81
#define L3GXXXX_XYZ_ENABLED (0x07)
83
#define L3GXXXX_ODR_S (6)
84
#define L3GXXXX_BW_S (4)
85
#define L3GXXXX_ODR_BW_S (4)
86
#define L3GXXXX_POWER_MODE_S (3)
87
#define L3GXXXX_Z_ENABLED_S (2)
88
#define L3GXXXX_Y_ENABLED_S (1)
89
#define L3GXXXX_X_ENABLED_S (1)
90
#define L3GXXXX_XYZ_ENABLED_S (0)
92
#define L3GXXXX_EXTR_EN (0x80)
93
#define L3GXXXX_LVL_EN (0x40)
94
#define L3GXXXX_HPF_MODE (0x30)
95
#define L3GXXXX_HPF_CUTOFF (0x0f)
97
#define L3GXXXX_EXTR_EN_S (7)
98
#define L3GXXXX_LVL_EN_S (6)
99
#define L3GXXXX_HPF_MODE_S (4)
101
#define L3GXXXX_INT1_IG (0x80)
102
#define L3GXXXX_INT1_BOOT (0x40)
103
#define L3GXXXX_HL_ACTIVE (0x20)
104
#define L3GXXXX_PP_OD (0x10)
105
#define L3GXXXX_INT2_DRDY (0x08)
106
#define L3GXXXX_INT2_WTM (0x04)
107
#define L3GXXXX_INT2_ORUN (0x02)
108
#define L3GXXXX_INT2_EMPTY (0x01)
110
#define L3GXXXX_INT1_IG_S (7)
111
#define L3GXXXX_INT1_BOOT_S (6)
112
#define L3GXXXX_HL_ACTIVE_S (5)
113
#define L3GXXXX_PP_OD_S (4)
114
#define L3GXXXX_INT2_DRDY_S (3)
115
#define L3GXXXX_INT2_WTM_S (2)
116
#define L3GXXXX_INT2_ORUN_S (1)
117
#define L3GXXXX_INT2_EMPTY_S (0)
119
#define L3GXXXX_BLOCK_DATA_UPDATE (0x80)
120
#define L3GXXXX_BIG_LITTLE_ENDIAN (0x40)
121
#define L3GXXXX_FULL_SCALE (0x30)
123
#define L3GXXXX_FULL_SCALE_S (4)
125
#define L3GXXXX_BOOT (0x80)
126
#define L3GXXXX_FIFO_EN (0x40)
127
#define L3GXXXX_STOP_ON_WTM (0x20)
128
#define L3GXXXX_HP_ENABLED (0x10)
129
#define L3GXXXX_IG_SEL (0x0c)
130
#define L3GXXXX_OUT_SEL (0x03)
132
#define L3GXXXX_BOOT_S (7)
133
#define L3GXXXX_FIFO_EN_S (6)
134
#define L3GXXXX_STOP_ON_WTM_S (5)
135
#define L3GXXXX_HP_ENABLED_S (4)
136
#define L3GXXXX_IG_SEL_S (2)
137
#define L3GXXXX_OUT_SEL_S (0)
139
#define L3GXXXX_FIFO_MODE (0xe0)
140
#define L3GXXXX_FIFO_WATERMARK (0x1f)
142
#define L3GXXXX_FIFO_MODE_S (5)
143
#define L3GXXXX_FIFO_WATERMARK_S (0)
145
#define L3GXXXX_FIFO_WTM (0x80)
146
#define L3GXXXX_FIFO_OVR (0x40)
147
#define L3GXXXX_FIFO_EMPTY (0x20)
148
#define L3GXXXX_FIFO_FFS (0x1f)
150
#define L3GXXXX_FIFO_WTM_S (7)
151
#define L3GXXXX_FIFO_OVR_S (6)
152
#define L3GXXXX_FIFO_EMPTY_S (5)
153
#define L3GXXXX_FIFO_FFS_S (0)
155
#define L3GXXXX_INT1_AND_OR (0x80)
156
#define L3GXXXX_INT1_LATCH (0x40)
157
#define L3GXXXX_INT1_Z_HIGH (0x20)
158
#define L3GXXXX_INT1_Z_LOW (0x10)
159
#define L3GXXXX_INT1_Y_HIGH (0x08)
160
#define L3GXXXX_INT1_Y_LOW (0x04)
161
#define L3GXXXX_INT1_X_HIGH (0x02)
162
#define L3GXXXX_INT1_X_LOW (0x01)
164
#define L3GXXXX_INT1_AND_OR_S (7)
165
#define L3GXXXX_INT1_LATCH_S (6)
166
#define L3GXXXX_INT1_Z_HIGH_S (5)
167
#define L3GXXXX_INT1_Z_LOW_S (4)
168
#define L3GXXXX_INT1_Y_HIGH_S (3)
169
#define L3GXXXX_INT1_Y_LOW_S (2)
170
#define L3GXXXX_INT1_X_HIGH_S (1)
171
#define L3GXXXX_INT1_X_LOW_S (0)
173
#define L3GXXXX_INT1_ACTIVE (0x40)
175
#define L3GXXXX_INT1_WAIT (0x80)
176
#define L3GXXXX_INT1_DURATION (0x3f)
178
#define L3GXXXX_INT1_WAIT_S (7)
179
#define L3GXXXX_INT1_DURATION_S (0)
181
#define L3GXXXX_DRDY_HL (0x20)
182
#define L3GXXXX_SW_RESET (0x04)
183
#define L3GXXXX_LOW_ODR (0x01)
185
#define L3GXXXX_DRDY_HL_S (5)
186
#define L3GXXXX_SW_RESET_S (2)
187
#define L3GXXXX_LOW_ODR_S (0)
191
#ifdef __cplusplus
192
}
193
#endif
194
195
#endif
/* L3GXXXX_REGS_H */
Generated on Sat Nov 23 2024 16:31:09 by
1.9.8