17#ifndef L3GXXXX_PARAMS_H
18#define L3GXXXX_PARAMS_H
32#if IS_USED(MODULE_L3GXXXX_I2C) || DOXYGEN
34#ifndef L3GXXXX_I2C_DEV
36#define L3GXXXX_I2C_DEV (I2C_DEV(0))
39#ifndef L3GXXXX_I2C_ADDR
41#define L3GXXXX_I2C_ADDR (L3GXXXX_I2C_ADDR_2)
44#ifndef L3GXXXX_I2C_IF_PARAMS
46#define L3GXXXX_I2C_IF_PARAMS .if_params.type = L3GXXXX_I2C, \
47 .if_params.i2c.dev = L3GXXXX_I2C_DEV, \
48 .if_params.i2c.addr = L3GXXXX_I2C_ADDR,
53#if IS_USED(MODULE_L3GXXXX_SPI) || DOXYGEN
55#ifndef L3GXXXX_SPI_DEV
57#define L3GXXXX_SPI_DEV SPI_DEV(0)
60#ifndef L3GXXXX_SPI_CLK
62#define L3GXXXX_SPI_CLK (SPI_CLK_1MHZ)
67#define L3GXXXX_SPI_CS (GPIO_PIN(0, 0))
70#ifndef L3GXXXX_SPI_IF_PARAMS
72#define L3GXXXX_SPI_IF_PARAMS .if_params.type = L3GXXXX_SPI, \
73 .if_params.spi.dev = L3GXXXX_SPI_DEV, \
74 .if_params.spi.clk = L3GXXXX_SPI_CLK, \
75 .if_params.spi.cs = L3GXXXX_SPI_CS,
80#ifndef L3GXXXX_INT1_PIN
82#define L3GXXXX_INT1_PIN (GPIO_PIN(0, 1))
85#ifndef L3GXXXX_INT2_PIN
87#define L3GXXXX_INT2_PIN (GPIO_PIN(0, 2))
99#ifdef CONFIG_L3GXXXX_ODR_100_12
100#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_100_12)
101#elif CONFIG_L3GXXXX_ODR_100_25
102#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_100_25)
103#elif CONFIG_L3GXXXX_ODR_200_12
104#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_200_12)
105#elif CONFIG_L3GXXXX_ODR_200_25
106#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_200_25)
107#elif CONFIG_L3GXXXX_ODR_200_50
108#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_200_50)
109#elif CONFIG_L3GXXXX_ODR_200_70
110#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_200_70)
111#elif CONFIG_L3GXXXX_ODR_400_20
112#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_400_20)
113#elif CONFIG_L3GXXXX_ODR_400_25
114#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_400_25)
115#elif CONFIG_L3GXXXX_ODR_400_50
116#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_400_50)
117#elif CONFIG_L3GXXXX_ODR_400_110
118#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_400_110)
119#elif CONFIG_L3GXXXX_ODR_800_30
120#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_800_30)
121#elif CONFIG_L3GXXXX_ODR_800_35
122#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_800_35)
123#elif CONFIG_L3GXXXX_ODR_800_50
124#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_800_50)
125#elif CONFIG_L3GXXXX_ODR_800_100
126#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_800_100)
127#elif CONFIG_L3GXXXX_ODR_12
128#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_12)
129#elif CONFIG_L3GXXXX_ODR_25
130#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_25)
131#elif CONFIG_L3GXXXX_ODR_50
132#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_50)
135#ifdef CONFIG_L3GXXXX_SCALE_245_DPS
136#define CONFIG_L3GXXXX_SCALE (L3GXXXX_SCALE_245_DPS)
137#elif CONFIG_L3GXXXX_SCALE_500_DPS
138#define CONFIG_L3GXXXX_SCALE (L3GXXXX_SCALE_500_DPS)
139#elif CONFIG_L3GXXXX_SCALE_2000_DPS
140#define CONFIG_L3GXXXX_SCALE (L3GXXXX_SCALE_2000_DPS)
143#ifdef CONFIG_L3GXXXX_NO_FILTER
144#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_NO_FILTER)
145#elif CONFIG_L3GXXXX_HPF_ONLY
146#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_HPF_ONLY)
147#elif CONFIG_L3GXXXX_LPF2_ONLY
148#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_LPF2_ONLY)
149#elif CONFIG_L3GXXXX_HPF_AND_LPF2
150#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_HPF_AND_LPF2)
153#ifdef CONFIG_L3GXXXX_HPF_NORMAL
154#define CONFIG_L3GXXXX_HPF_MODE (L3GXXXX_HPF_NORMAL)
155#elif CONFIG_L3GXXXX_HPF_REFERENCE
156#define CONFIG_L3GXXXX_HPF_MODE (L3GXXXX_HPF_REFERENCE)
157#elif CONFIG_L3GXXXX_HPF_AUTORESET
158#define CONFIG_L3GXXXX_HPF_MODE (L3GXXXX_HPF_AUTORESET)
161#ifdef CONFIG_L3GXXXX_FIFO_MODE_BYPASS
162#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_BYPASS)
163#elif CONFIG_L3GXXXX_FIFO_MODE_FIFO
164#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_FIFO)
165#elif CONFIG_L3GXXXX_FIFO_MODE_STREAM
166#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_STREAM)
167#elif CONFIG_L3GXXXX_FIFO_MODE_STREAM_TO_FIFO
168#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_STREAM_TO_FIFO)
169#elif CONFIG_L3GXXXX_FIFO_MODE_BYPASS_TO_STREAM
170#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_BYPASS_TO_STREAM)
171#elif CONFIG_L3GXXXX_FIFO_MODE_DYNAMIC_STREAM
172#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_DYNAMIC_STREAM
173#elif CONFIG_L3GXXXX_FIFO_MODE_BYPASS_TO_FIFO
174#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_BYPASS_TO_FIFO)
177#ifdef CONFIG_L3GXXXX_INT1_NO_FILTER
178#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_NO_FILTER)
179#elif CONFIG_L3GXXXX_INT1_HPF_ONLY
180#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_HPF_ONLY)
181#elif CONFIG_L3GXXXX_INT1_LPF2_ONLY
182#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_LPF2_ONLY)
183#elif CONFIG_L3GXXXX_INT1_HPF_AND_LPF2
184#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_HPF_AND_LPF2)
189#ifndef CONFIG_L3GXXXX_ODR
191#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_100_25)
194#ifndef CONFIG_L3GXXXX_SCALE
196#define CONFIG_L3GXXXX_SCALE (L3GXXXX_SCALE_245_DPS)
199#ifndef CONFIG_L3GXXXX_FILTER_SEL
201#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_HPF_AND_LPF2)
204#ifndef CONFIG_L3GXXXX_HPF_MODE
206#define CONFIG_L3GXXXX_HPF_MODE (L3GXXXX_HPF_NORMAL)
209#ifndef CONFIG_L3GXXXX_HPF_CUTOFF
211#define CONFIG_L3GXXXX_HPF_CUTOFF (0)
214#ifndef CONFIG_L3GXXXX_FIFO_MODE
216#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_FIFO)
219#ifndef CONFIG_L3GXXXX_FIFO_WATERMARK
221#define CONFIG_L3GXXXX_FIFO_WATERMARK (23)
224#ifndef CONFIG_L3GXXXX_INT1_X_THRESH
226#define CONFIG_L3GXXXX_INT1_X_THRESH (4012)
229#ifndef CONFIG_L3GXXXX_INT1_X_GT_THRESH
231#define CONFIG_L3GXXXX_INT1_X_GT_THRESH (true)
234#ifndef CONFIG_L3GXXXX_INT1_X_LT_THRESH
236#define CONFIG_L3GXXXX_INT1_X_LT_THRESH (false)
239#ifndef CONFIG_L3GXXXX_INT1_Y_THRESH
241#define CONFIG_L3GXXXX_INT1_Y_THRESH (4012)
244#ifndef CONFIG_L3GXXXX_INT1_Y_GT_THRESH
246#define CONFIG_L3GXXXX_INT1_Y_GT_THRESH (true)
249#ifndef CONFIG_L3GXXXX_INT1_Y_LT_THRESH
251#define CONFIG_L3GXXXX_INT1_Y_LT_THRESH (false)
254#ifndef CONFIG_L3GXXXX_INT1_Z_THRESH
256#define CONFIG_L3GXXXX_INT1_Z_THRESH (4012)
259#ifndef CONFIG_L3GXXXX_INT1_Z_GT_THRESH
261#define CONFIG_L3GXXXX_INT1_Z_GT_THRESH (true)
264#ifndef CONFIG_L3GXXXX_INT1_Z_LT_THRESH
266#define CONFIG_L3GXXXX_INT1_Z_LT_THRESH (false)
269#ifndef CONFIG_L3GXXXX_INT1_FILTER
271#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_HPF_AND_LPF2)
274#ifndef CONFIG_L3GXXXX_INT1_AND
276#define CONFIG_L3GXXXX_INT1_AND (false)
279#ifndef CONFIG_L3GXXXX_INT1_LATCH
281#define CONFIG_L3GXXXX_INT1_LATCH (true)
284#if IS_USED(MODULE_L3GXXXX_IRQ_EVENT) || DOXYGEN
286#define L3GXXXX_INT1_PARAMS .int1_pin = L3GXXXX_INT1_PIN, \
287 .int1_cfg.x_high_enabled = CONFIG_L3GXXXX_INT1_X_GT_THRESH, \
288 .int1_cfg.y_high_enabled = CONFIG_L3GXXXX_INT1_Y_GT_THRESH, \
289 .int1_cfg.z_high_enabled = CONFIG_L3GXXXX_INT1_Z_GT_THRESH, \
290 .int1_cfg.x_low_enabled = CONFIG_L3GXXXX_INT1_X_LT_THRESH, \
291 .int1_cfg.y_low_enabled = CONFIG_L3GXXXX_INT1_Y_LT_THRESH, \
292 .int1_cfg.z_low_enabled = CONFIG_L3GXXXX_INT1_Z_LT_THRESH, \
293 .int1_cfg.x_threshold = CONFIG_L3GXXXX_INT1_X_THRESH, \
294 .int1_cfg.y_threshold = CONFIG_L3GXXXX_INT1_Y_THRESH, \
295 .int1_cfg.z_threshold = CONFIG_L3GXXXX_INT1_Z_THRESH, \
296 .int1_cfg.filter = CONFIG_L3GXXXX_INT1_FILTER, \
297 .int1_cfg.and_or = CONFIG_L3GXXXX_INT1_AND, \
298 .int1_cfg.latch = CONFIG_L3GXXXX_INT1_LATCH,
300#define L3GXXXX_INT1_PARAMS
303#if IS_USED(MODULE_L3GXXXX_IRQ_DATA) || DOXYGEN
305#define L3GXXXX_INT2_PARAMS .int2_pin = L3GXXXX_INT2_PIN,
307#define L3GXXXX_INT2_PARAMS
310#if IS_USED(MODULE_L3GXXXX_FIFO) || DOXYGEN
312#define L3GXXXX_FIFO_PARAMS .fifo_mode = CONFIG_L3GXXXX_FIFO_MODE, \
313 .fifo_watermark = CONFIG_L3GXXXX_FIFO_WATERMARK,
315#define L3GXXXX_FIFO_PARAMS
318#if IS_USED(MODULE_L3GXXXX_I2C) || DOXYGEN
320#ifndef L3GXXXX_I2C_PARAMS
322#define L3GXXXX_I2C_PARAMS { \
323 L3GXXXX_I2C_IF_PARAMS \
324 .odr = CONFIG_L3GXXXX_ODR, \
325 .scale = CONFIG_L3GXXXX_SCALE, \
326 .filter_sel = CONFIG_L3GXXXX_FILTER_SEL, \
327 .hpf_mode = CONFIG_L3GXXXX_HPF_MODE, \
328 .hpf_cutoff = CONFIG_L3GXXXX_HPF_CUTOFF, \
329 L3GXXXX_FIFO_PARAMS \
330 L3GXXXX_INT1_PARAMS \
331 L3GXXXX_INT2_PARAMS \
336#if IS_USED(MODULE_L3GXXXX_SPI) || DOXYGEN
337#ifndef L3GXXXX_SPI_PARAMS
339#define L3GXXXX_SPI_PARAMS { \
340 L3GXXXX_SPI_IF_PARAMS \
341 .odr = CONFIG_L3GXXXX_ODR, \
342 .scale = CONFIG_L3GXXXX_SCALE, \
343 .filter_sel = CONFIG_L3GXXXX_FILTER_SEL, \
344 .hpf_mode = CONFIG_L3GXXXX_HPF_MODE, \
345 .hpf_cutoff = CONFIG_L3GXXXX_HPF_CUTOFF, \
346 L3GXXXX_FIFO_PARAMS \
347 L3GXXXX_INT1_PARAMS \
348 L3GXXXX_INT2_PARAMS \
353#ifndef L3GXXXX_SAUL_INFO
355#define L3GXXXX_SAUL_INFO { .name = "l3gxxxx" }
364#if IS_USED(MODULE_L3GXXXX_I2C) || DOXYGEN
367#if IS_USED(MODULE_L3GXXXX_SPI) || DOXYGEN
Device Driver for ST L3Gxxxx 3-axis gyroscope sensor family.
static const l3gxxxx_params_t l3gxxxx_params[]
Allocate some memory to store the actual configuration.
#define L3GXXXX_SAUL_INFO
Default SAUL device info.
static const saul_reg_info_t l3gxxxx_saul_info[]
Additional meta information to keep in the SAUL registry.
#define L3GXXXX_I2C_PARAMS
Default I2C device parameter set.
#define L3GXXXX_SPI_PARAMS
Default SPI device parameter set.
SAUL registry interface definition.
L3Gxxxx device initialization parameters.
Additional data to collect for each entry.