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cpu_conf_kinetis_w.h
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1/*
2 * Copyright (C) 2017 Eistec AB
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser General
5 * Public License v2.1. See the file LICENSE in the top level directory for more
6 * details.
7 */
8
21#ifndef CPU_CONF_KINETIS_W_H
22#define CPU_CONF_KINETIS_W_H
23
24#if defined(KINETIS_CORE_D)
25/* Kinetis KW2xD */
26#if defined(CPU_MODEL_MKW21D256VHA5) || \
27 defined(CPU_MODEL_MKW21D512VHA5)
28#include "vendor/MKW21D5.h"
29#elif defined(CPU_MODEL_MKW22D512VHA5)
30#include "vendor/MKW22D5.h"
31#elif defined(CPU_MODEL_MKW24D512VHA5)
32#include "vendor/MKW24D5.h"
33#endif
34
38#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
44#define KW2XDRF_PORT_DEV PORTB
45#define KW2XDRF_PORT PORT_B
46#define KW2XDRF_GPIO GPIOB
47#define KW2XDRF_PORT_IRQn PORTB_IRQn
49#define KW2XDRF_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
50#define KW2XDRF_PIN_AF 2
51#define KW2XDRF_PCS0_PIN 10
52#define KW2XDRF_SCK_PIN 11
53#define KW2XDRF_SOUT_PIN 16
54#define KW2XDRF_SIN_PIN 17
55#define KW2XDRF_RST_PIN 19
56#define KW2XDRF_IRQ_PIN 3
57#define KW2XDRF_CLK_CTRL_PORT PORT_C
58#define KW2XDRF_CLK_CTRL_PORT_DEV PORTC
59#define KW2XDRF_CLK_CTRL_GPIO GPIOC
60#define KW2XDRF_CLK_CTRL_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
61#define KW2XDRF_CLK_CTRL_PIN 0
64#elif defined(KINETIS_CORE_Z)
65/* Kinetis KWxxZ */
66#if defined(CPU_MODEL_MKW21Z256VHT4) || \
67 defined(CPU_MODEL_MKW21Z512VHT4)
68#include "vendor/MKW21Z4.h"
69#elif defined(CPU_MODEL_MKW31Z256VHT4) || \
70 defined(CPU_MODEL_MKW31Z512CAT4) || \
71 defined(CPU_MODEL_MKW31Z512VHT4)
72#include "vendor/MKW31Z4.h"
73#elif defined(CPU_MODEL_MKW41Z256VHT4) || \
74 defined(CPU_MODEL_MKW41Z512CAT4) || \
75 defined(CPU_MODEL_MKW41Z512VHT4)
76#include "vendor/MKW41Z4.h"
77#endif
78#endif /* KINETIS_CORE_x */
79
84#define FLASHPAGE_SIZE (2048U)
85#define FLASHPAGE_NUMOF ((KINETIS_ROMSIZE * 1024) / FLASHPAGE_SIZE)
86
87/* The minimum block size which can be written is 4B. However, the erase
88 * block is always FLASHPAGE_SIZE.
89 */
90#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
91/* Writing should be always 4 bytes aligned */
92#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
93/* Section erase and programming must be 8 bytes aligned */
94#define FLASHPAGE_BLOCK_SECTION_ALIGNMENT (8U)
97#ifdef __cplusplus
98extern "C"
99{
100#endif
101
102#ifdef __cplusplus
103}
104#endif
105
106#endif /* CPU_CONF_KINETIS_W_H */