Toggle navigation
Documentation
The friendly Operating System for the Internet of Things
Loading...
Searching...
No Matches
cc26xx_cc13xx_wdt.h
Go to the documentation of this file.
1
/*
2
* Copyright (C) 2016 Leon George
3
*
4
* This file is subject to the terms and conditions of the GNU Lesser
5
* General Public License v2.1. See the file LICENSE in the top level
6
* directory for more details.
7
*/
8
17
#ifndef CC26XX_CC13XX_WDT_H
18
#define CC26XX_CC13XX_WDT_H
19
20
#include <
cc26xx_cc13xx.h
>
21
22
#ifdef __cplusplus
23
extern
"C"
{
24
#endif
25
29
typedef
struct
{
30
reg32_t
LOAD
;
31
reg32_t
VALUE
;
32
reg32_t
CTL
;
33
reg32_t
ICR
;
34
reg32_t
RIS
;
35
reg32_t
MIS
;
36
reg32_t
__reserved1[0x100];
37
reg32_t
TEST
;
38
reg32_t
INT_CAUS
;
39
reg32_t
__reserved2[0x1f9];
40
reg32_t
LOCK
;
41
}
wdt_regs_t
;
42
47
#define WDT_BASE 0x40080000
50
#define WDT ((wdt_regs_t *) (WDT_BASE))
52
#ifdef __cplusplus
53
}
/* end extern "C" */
54
#endif
55
56
#endif
/* CC26XX_CC13XX_WDT_H */
cc26xx_cc13xx.h
CC26xx, CC13xx definitions.
reg32_t
volatile uint32_t reg32_t
Unsigned 32-bit register type.
Definition
cc26xx_cc13xx.h:40
wdt_regs_t
WDT registers.
Definition
cc26xx_cc13xx_wdt.h:29
wdt_regs_t::LOCK
reg32_t LOCK
lock
Definition
cc26xx_cc13xx_wdt.h:40
wdt_regs_t::INT_CAUS
reg32_t INT_CAUS
interrupt cause test mode
Definition
cc26xx_cc13xx_wdt.h:38
wdt_regs_t::CTL
reg32_t CTL
control
Definition
cc26xx_cc13xx_wdt.h:32
wdt_regs_t::ICR
reg32_t ICR
interrupt clear
Definition
cc26xx_cc13xx_wdt.h:33
wdt_regs_t::VALUE
reg32_t VALUE
current count value
Definition
cc26xx_cc13xx_wdt.h:31
wdt_regs_t::LOAD
reg32_t LOAD
config
Definition
cc26xx_cc13xx_wdt.h:30
wdt_regs_t::MIS
reg32_t MIS
masked interrupt status
Definition
cc26xx_cc13xx_wdt.h:35
wdt_regs_t::TEST
reg32_t TEST
test mode
Definition
cc26xx_cc13xx_wdt.h:37
wdt_regs_t::RIS
reg32_t RIS
raw interrupt status
Definition
cc26xx_cc13xx_wdt.h:34
Generated on Sat Nov 23 2024 01:58:06 by
1.9.8