at86rf2xx_internal.h

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/*
 * SPDX-FileCopyrightText: 2013 Alaeddine Weslati <alaeddine.weslati@inria.fr>
 * SPDX-FileCopyrightText: 2015 Freie Universität Berlin
 * SPDX-FileCopyrightText: 2017 HAW Hamburg
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include <stdint.h>
 
#include "at86rf2xx.h"
 
#if AT86RF2XX_IS_PERIPH
#  include <string.h>
#  include "irq.h"
#  include "time_units.h"
#endif
#include "at86rf2xx_registers.h"
 
#ifdef __cplusplus
extern "C" {
#endif

#ifdef MODULE_AT86RF212B
#  define AT86RF2XX_TXPOWER_MAX_INDEX           (36)
#elif MODULE_AT86RF233
#  define AT86RF2XX_TXPOWER_MAX_INDEX           (21)
#else
#  define AT86RF2XX_TXPOWER_MAX_INDEX           (20)
#endif

#ifdef MODULE_AT86RF212B
#  define AT86RF2XX_TXPOWER_OFF_OFFSET           (25)
#else
#  define AT86RF2XX_TXPOWER_OFF_OFFSET           (17)
#endif

#define AT86RF2XX_WAKEUP_DELAY          (306U)

#define AT86RF2XX_RESET_PULSE_WIDTH     (62U)

#define AT86RF2XX_RESET_DELAY           (62U)

#if AT86RF2XX_IS_PERIPH
static inline uint8_t at86rf2xx_reg_read(const at86rf2xx_t *dev, volatile uint8_t *addr) {
    (void) dev;
    return *addr;
}
#else
uint8_t at86rf2xx_reg_read(const at86rf2xx_t *dev, uint8_t addr);
#endif

#if AT86RF2XX_IS_PERIPH
static inline void at86rf2xx_reg_write(const at86rf2xx_t *dev, volatile uint8_t *addr,
                                       const uint8_t value) {
    (void) dev;
    *addr = value;
}
#else
void at86rf2xx_reg_write(const at86rf2xx_t *dev, uint8_t addr, uint8_t value);
#endif

#if AT86RF2XX_IS_PERIPH
static inline void at86rf2xx_sram_read(const at86rf2xx_t *dev, uint8_t offset,
                                       uint8_t *data, size_t len) {
    (void)dev;
    memcpy(data, (void*)(AT86RF2XX_REG__TRXFBST + offset), len);
}
#else
void at86rf2xx_sram_read(const at86rf2xx_t *dev, uint8_t offset,
                         uint8_t *data, size_t len);
#endif
#if AT86RF2XX_IS_PERIPH
static inline void at86rf2xx_sram_write(const at86rf2xx_t *dev, uint8_t offset,
                                        const uint8_t *data, size_t len) {
    (void)dev;
    memcpy((void*)(AT86RF2XX_REG__TRXFBST + offset), data, len);
}
#else
void at86rf2xx_sram_write(const at86rf2xx_t *dev, uint8_t offset,
                          const uint8_t *data, size_t len);
#endif
#if AT86RF2XX_IS_PERIPH
static inline void at86rf2xx_fb_start(const at86rf2xx_t *dev) {
    (void) dev;
}
#else
void at86rf2xx_fb_start(const at86rf2xx_t *dev);
#endif
#if AT86RF2XX_IS_PERIPH
static inline void at86rf2xx_fb_read(const at86rf2xx_t *dev, uint8_t *data, size_t len) {
    (void)dev;
    memcpy(data, (void*)AT86RF2XX_REG__TRXFBST, len);
}
#else
void at86rf2xx_fb_read(const at86rf2xx_t *dev, uint8_t *data, size_t len);
#endif
#if AT86RF2XX_IS_PERIPH
static inline void at86rf2xx_fb_stop(const at86rf2xx_t *dev) {
    (void) dev;
}
#else
void at86rf2xx_fb_stop(const at86rf2xx_t *dev);
#endif
uint8_t at86rf2xx_get_status(const at86rf2xx_t *dev);

void at86rf2xx_assert_awake(at86rf2xx_t *dev);

void at86rf2xx_hardware_reset(at86rf2xx_t *dev);

void at86rf2xx_configure_phy(at86rf2xx_t *dev, uint8_t chan, ieee802154_phy_mode_t mode,
                             int16_t txpower);
 
#if AT86RF2XX_RANDOM_NUMBER_GENERATOR || defined(DOXYGEN)
void at86rf2xx_get_random(at86rf2xx_t *dev, uint8_t *data, size_t len);
#endif

void at86rf2xx_spi_init(at86rf2xx_t *dev, void (*irq_handler)(void *arg), void *ctx);

static inline uint8_t at86rf2xx_get_rx_len(at86rf2xx_t *dev)
{
    (void) dev;
#if AT86RF2XX_IS_PERIPH
    return TST_RX_LENGTH;
#else
    uint8_t phr;
    at86rf2xx_fb_read(dev, &phr, 1);
    return phr;
#endif
}

static inline uint8_t at86rf2xx_peek_rx_len(at86rf2xx_t *dev)
{
    (void) dev;
#if AT86RF2XX_IS_PERIPH
    return TST_RX_LENGTH;
#else
    uint8_t phr;
    at86rf2xx_fb_start(dev);
    phr = at86rf2xx_get_rx_len(dev);
    at86rf2xx_fb_stop(dev);
    return phr;
#endif
}
 
#if AT86RF2XX_IS_PERIPH
/*
 * Read a 32 bit register as described in section 10.3 of the datasheet: A read
 * of the least significant byte causes the current value to be atomically
 * captured in a temporary 32 bit registers. The remaining reads will access this
 * register instead. Only a single 32 bit temporary register is used to provide
 * means to atomically access them. Thus, interrupts must be disabled during the
 * read sequence in order to prevent other threads (or ISRs) from updating the
 * temporary 32 bit register before the reading sequence has completed.
 */
static inline uint32_t reg32_read(volatile uint8_t *reg_ll)
{
    le_uint32_t reg;
    unsigned state = irq_disable();
    reg.u8[0] =  reg_ll[0];
    reg.u8[1] =  reg_ll[1];
    reg.u8[2] =  reg_ll[2];
    reg.u8[3] =  reg_ll[3];
    irq_restore(state);
    return reg.u32;
}

static inline uint32_t at86rf2xx_get_sc(const at86rf2xx_t *dev)
{
    (void) dev;
    return reg32_read(&SCCNTLL);
}
 
/* Symbol counter frequency is 62500Hz. One symbol counter tick is 16us = 16000 ns*/
#define SC_TO_NS (16000LU)
 
#endif
 
#ifdef __cplusplus
}
#endif