40#ifndef ADS1X1X_PARAM_I2C
41# define ADS1X1X_PARAM_I2C (I2C_DEV(0))
48#ifndef CONFIG_ADS1X1X_I2C_ADDR
49# define CONFIG_ADS1X1X_I2C_ADDR (0x48)
56#if IS_ACTIVE(CONFIG_ADS1X1X_MUX_AIN0_DIFFM_AIN1)
57# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN0_DIFFM_AIN1)
58#elif IS_ACTIVE(CONFIG_ADS1X1X_MUX_AIN0_DIFFM_AIN3)
59# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN0_DIFFM_AIN3)
60#elif IS_ACTIVE(CONFIG_ADS1X1X_MUX_AIN1_DIFFM_AIN3)
61# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN1_DIFFM_AIN3)
62#elif IS_ACTIVE(CONFIG_ADS1X1X_MUX_AIN2_DIFFM_AIN3)
63# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN2_DIFFM_AIN3)
64#elif IS_ACTIVE(CONFIG_ADS1X1X1_MUX_AIN0_SINGM)
65# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN0_SINGM)
66#elif IS_ACTIVE(CONFIG_ADS1X1X_MUX_AIN1_SINGM)
67# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN1_SINGM)
68#elif IS_ACTIVE(CONFIG_ADS1X1X_MUX_AIN2_SINGM)
69# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN2_SINGM)
70#elif IS_ACTIVE(CONFIG_ADS1X1X_MUX_AIN3_SINGM)
71# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN3_SINGM)
74#ifndef ADS1X1X_PARAM_MUX
75# define ADS1X1X_PARAM_MUX (ADS1X1X_AIN0_DIFFM_AIN1)
82#ifndef ADS1X1X_PARAM_ALERT_PIN
83# define ADS1X1X_PARAM_ALERT_PIN (GPIO_UNDEF)
90#ifndef CONFIG_ADS1X1X_LOW_LIMIT
91# define CONFIG_ADS1X1X_LOW_LIMIT (10000U)
98#ifndef CONFIG_ADS1X1X_HIGH_LIMIT
99# define CONFIG_ADS1X1X_HIGH_LIMIT (20000U)
106#if IS_ACTIVE(CONFIG_ADS1X1X_PGA_FSR_6V144)
107# define ADS1X1X_PARAM_PGA (ADS1X1X_PGA_FSR_6V144)
108#elif IS_ACTIVE(CONFIG_ADS1X1X_PGA_FSR_4V096)
109# define ADS1X1X_PARAM_PGA (ADS1X1X_PGA_FSR_4V096)
110#elif IS_ACTIVE(CONFIG_ADS1X1X_PGA_FSR_2V048)
111# define ADS1X1X_PARAM_PGA (ADS1X1X_PGA_FSR_2V048)
112#elif IS_ACTIVE(CONFIG_ADS1X1X_PGA_FSR_1V024)
113# define ADS1X1X_PARAM_PGA (ADS1X1X_PGA_FSR_1V024)
114#elif IS_ACTIVE(CONFIG_ADS1X1X_PGA_FSR_0V512)
115# define ADS1X1X_PARAM_PGA (ADS1X1X_PGA_FSR_0V512)
116#elif IS_ACTIVE(CONFIG_ADS1X1X_PGA_FSR_0V256)
117# define ADS1X1X_PARAM_PGA (ADS1X1X_PGA_FSR_0V256)
120#ifndef ADS1X1X_PARAM_PGA
121# define ADS1X1X_PARAM_PGA (ADS1X1X_PGA_FSR_2V048)
128#ifndef ADS1X1X_PARAM_DATAR
129# define ADS1X1X_PARAM_DATAR ADS1X1X_DATAR_UNDEF
136#if IS_ACTIVE(CONFIG_ADS1X1X_MODE_SINGLE)
137# define ADS1X1X_PARAM_MODE (ADS1X1X_MODE_SINGLE)
138#elif IS_ACTIVE(CONFIG_ADS1X1X_MODE_CONTINUOUS)
139# define ADS1X1X_PARAM_MODE (ADS1X1X_MODE_CONTINUOUS)
142#ifndef ADS1X1X_PARAM_MODE
143# define ADS1X1X_PARAM_MODE (ADS1X1X_MODE_SINGLE)
150#if IS_ACTIVE(CONFIG_ADS1X1X_COMP_MODE_TRADITIONAL)
151# define ADS1X1X_PARAM_COMP_MODE (ADS1X1X_COMP_MODE_TRADITIONAL)
152#elif IS_ACTIVE(CONFIG_ADS1X1X_COMP_MODE_WINDOW)
153# define ADS1X1X_PARAM_COMP_MODE (ADS1X1X_COMP_MODE_WINDOW)
156#ifndef ADS1X1X_PARAM_COMP_MODE
157# define ADS1X1X_PARAM_COMP_MODE (ADS1X1X_COMP_MODE_TRADITIONAL)
164#if IS_ACTIVE(CONFIG_ADS1X1X_COMP_POLARITY_LOW)
165# define ADS1X1X_PARAM_COMP_POLARITY (ADS1X1X_COMP_POLARITY_LOW)
166#elif IS_ACTIVE(CONFIG_ADS1X1X_COMP_POLARITY_HIGH)
167# define ADS1X1X_PARAM_COMP_POLARITY (ADS1X1X_COMP_POLARITY_HIGH)
170#ifndef ADS1X1X_PARAM_COMP_POLARITY
171# define ADS1X1X_PARAM_COMP_POLARITY (ADS1X1X_COMP_POLARITY_LOW)
178#if IS_ACTIVE(CONFIG_ADS1X1X_COMP_LATCH_DISABLE)
179# define ADS1X1X_PARAM_COMP_LATCH (ADS1X1X_COMP_LATCH_DISABLE)
180#elif IS_ACTIVE(CONFIG_ADS1X1X_COMP_LATCH_ENABLE)
181# define ADS1X1X_PARAM_COMP_LATCH (ADS1X1X_COMP_LATCH_ENABLE)
184#ifndef ADS1X1X_PARAM_COMP_LATCH
185# define ADS1X1X_PARAM_COMP_LATCH (ADS1X1X_COMP_LATCH_DISABLE)
192#if IS_ACTIVE(CONFIG_ADS1X1X_COMP_QUEUE_1)
193# define ADS1X1X_PARAM_COMP_QUEUE (ADS1X1X_COMP_QUEUE_1)
194#elif IS_ACTIVE(CONFIG_ADS1X1X_COMP_QUEUE_2)
195# define ADS1X1X_PARAM_COMP_QUEUE (ADS1X1X_COMP_QUEUE_2)
196#elif IS_ACTIVE(CONFIG_ADS1X1X_COMP_QUEUE_4)
197# define ADS1X1X_PARAM_COMP_QUEUE (ADS1X1X_COMP_QUEUE_4)
198#elif IS_ACTIVE(CONFIG_ADS1X1X_COMP_QUEUE_DISABLE)
199# define ADS1X1X_PARAM_COMP_QUEUE (ADS1X1X_COMP_QUEUE_DISABLE)
202#ifndef ADS1X1X_PARAM_COMP_QUEUE
203# define ADS1X1X_PARAM_COMP_QUEUE (ADS1X1X_COMP_QUEUE_DISABLE)
210#ifndef ADS1X1X_PARAM_BITS_RES
211# define ADS1X1X_PARAM_BITS_RES (ADS1X1X_BITS_RES_UNDEF)
236#ifndef ADS1X1X_PARAMS
237# define ADS1X1X_PARAMS { .i2c = ADS1X1X_PARAM_I2C, \
238 .addr = CONFIG_ADS1X1X_I2C_ADDR, \
239 .mux = ADS1X1X_PARAM_MUX, \
240 .pga = ADS1X1X_PARAM_PGA, \
241 .mode = ADS1X1X_PARAM_MODE, \
242 .dr = ADS1X1X_PARAM_DATAR, \
243 .bits_res = ADS1X1X_PARAM_BITS_RES }
250#ifndef ADS1X1X_ALERT_PARAMS
251# define ADS1X1X_ALERT_PARAMS { .i2c = ADS1X1X_PARAM_I2C, \
252 .addr = CONFIG_ADS1X1X_I2C_ADDR, \
253 .comp_mode = ADS1X1X_PARAM_COMP_MODE, \
254 .comp_polarity = ADS1X1X_PARAM_COMP_POLARITY, \
255 .comp_latch = ADS1X1X_PARAM_COMP_LATCH, \
256 .comp_queue = ADS1X1X_PARAM_COMP_QUEUE, \
257 .alert_pin = ADS1X1X_PARAM_ALERT_PIN, \
258 .low_limit = CONFIG_ADS1X1X_LOW_LIMIT, \
259 .high_limit = CONFIG_ADS1X1X_HIGH_LIMIT }
266#ifndef ADS1X1X_SAUL_INFO
267# define ADS1X1X_SAUL_INFO { .name = "ads1x1x" }
ADS101x/111x ADC device driver.
Internal definitions for ADS101x/111x devices.
#define ADS1X1X_ALERT_PARAMS
Default ADS1X1X alert parameters structure.
#define ADS1X1X_PARAMS
Default configuration parameters structure for ADS1X1X ADC devices.
#define ADS1X1X_SAUL_INFO
Additional SAUL registry information.
static const ads1x1x_params_t ads1x1x_params[]
ADS1X1X defaults if not defined for a board or application.
static const saul_reg_info_t ads1x1x_saul_info[]
Additional meta information to keep in the SAUL registry.
struct ads1x1x_alert_params ads1x1x_alert_params_t
ADS101x/111x alert params.
Low-level I2C peripheral driver interface definition.
SAUL registry interface definition.
ADS101x/111x alert params.
Additional data to collect for each entry.